參數(shù)資料
型號(hào): BX80532KE2000D
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 2000 MHz, MICROPROCESSOR, XMA
文件頁數(shù): 11/102頁
文件大小: 1464K
代理商: BX80532KE2000D
16
Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz
2.6
Voltage Identification
The VID specification for the processor is defined in this datasheet, and is supported by power
delivery solutions designed according to the Dual Intel Xeon TM Processor Voltage Regulator
Down (VRD) Design Guidelines, VRM 9.0 DC-DC Converter Design Guidelines, and VRM 9.1
DC-DC Converter Design Guidelines. The minimum voltage is provided in Table 6, and varies
with processor frequency. This allows processors running at a higher frequency to have a relaxed
minimum voltage specification. The specifications have been set such that one voltage regulator
design can work with all supported processor frequencies.
Note that the VID pins will drive valid and correct logic levels when the Intel Xeon processor
with 533 MHz Front Side Bus is provided with a valid voltage applied to the SM_VCC pins.
VID_VCC must be correct and stable prior to enabling the output of the VRM that supplies
VCC. Similarly, the output of the VRM must be disabled before VID_VCC becomes invalid.
Refer to Figure 17 for details.
The processor uses five voltage identification pins, VID[4:0], to support automatic selection of
processor voltages. Table 3 specifies the voltage level corresponding to the state of VID[4:0]. A ‘1’
in this table refers to a high voltage and a ‘0’ refers to low voltage level. If the processor socket is
empty (VID[4:0] = 11111), or the VRD or VRM cannot supply the voltage that is requested, it must
disable its voltage output. For further details, see the Dual Intel XeonTM Processor Voltage
Regulator Down (VRD) Design Guidelines, or VRM 9.0 DC-DC Converter Design Guidelines or
the VRM 9.1 DC-DC Converter Design Guidelines.
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