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參數(shù)資料
| 型號(hào)： | BX80526F900128 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 900 MHz, MICROPROCESSOR, CPGA370 |
| 封裝： | FLIP CHIP, PGA-370 |
| 文件頁(yè)數(shù)： | 31/130頁(yè) |
| 文件大?。?/td> | 2654K |
| 代理商： | BX80526F900128 |
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126
Datasheet
Intel Celeron Processor up to 1.10 GHz
7.1
Signal Summaries
VCOREDET
(PGA packages
only)
O
The VCOREDET signal will float for 2.0 V core processors and will be grounded for the
Celeron FC-PGA/FC-PGA2 processor with a 1.5V core voltage.
VID[4:0]
(S.E.P.P.)
VID[3:0]
(PGA packages
only)
O
The VID (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to VSS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on Intel Celeron processors. See Table 2 for
definitions of these pins. The power supply must supply the voltage that is requested
by these pins, or disable itself.
VREF[7:0]
(PGA packages
only)
I
These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+
inputs are differential receivers and will use this voltage to determine whether the
signal is a logic high or logic low.
For the FC-PGA/FC-PGA2 packages, VREF is typically 2/3 of VTT
Table 59. Alphabetical Signal Reference (Sheet 7 of 7)
Signal
Type
Description
Table 60. Output Signals
Name
Active Level
Clock
Signal Group
CPUPRES# (PGA
packages only)
Low
Asynch
Power/Other
FERR#
Low
Asynch
CMOS Output
IERR#
Low
Asynch
CMOS Output
PRDY#
Low
BCLK
AGTL+ Output
SLOTOCC#
(S.E.P.P. only)
Low
Asynch
Power/Other
TDO
High
TCK
TAP Output
THERMDN
N/A
Asynch
Power/Other
THERMTRIP#
Low
Asynch
CMOS Output
VCOREDET
(PGA packages only)
High
Asynch
Power/Other
VID[4:0] (S.E.P.P.)
VID[3:0] (PGA
packages)
High
Asynch
Power/Other
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