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參數(shù)資料
| 型號： | BX80526F1000128 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA370 |
| 封裝： | FLIP CHIP, PGA-370 |
| 文件頁數(shù)： | 26/130頁 |
| 文件大?。?/td> | 2654K |
| 代理商： | BX80526F1000128 |
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Datasheet
121
Intel Celeron Processor up to 1.10 GHz
BPRI#
I
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
Intel Celeron processor system bus. It must connect the appropriate pins of all Intel
Celeron processor system bus agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new requests, unless such
requests are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed, then releases the bus by deasserting
BPRI#.
BSEL[1:0]
I/O
These signals are used to select the system bus frequency. The frequency is
determined by the processor(s), chipset, and frequency synthesizer capabilities. All
system bus agents must operate at the same frequency. Individual processors will
only operate at their specified front side bus (FSB) frequency. On motherboards
which support operation at either 66 MHz or 100 MHz, a BSEL[1:0] = “x1” will select
a 100 MHz system bus frequency and a BSEL[1:0] = “x0” will select a 66 MHz
system bus frequency.
These signals must be pulled up to 2.5 V or 3.3 V with 1 K
resistor and provided as
a frequency selection signal to the clock driver/synthesizer. See Section 2.7.2 for
implementation examples.
note: BSEL1 is not used by the Celeron processor.
BR0#
I/O
The BR0# (Bus Request) pin drives the BREQ[0]# signal in the system. During
power-up configuration, the central agent asserts the BREQ0# bus signal in the
system to assign the symmetric agent ID to the processor. The processor samples
it’s BR0# pin on the active-to-inactive transition of RESET# to obtain it’s symmetric
agent ID. The processor asserts BR0# to request the system bus.
CPUPRES#
(PPGA,
FC-PGA/
FC-PGA2 only)
O
The CPUPRES# signal provides the ability for a system board to detect the
presence of a processor. This pin is a ground on the processor indicating to the
system that a processor is installed.
Combined with the VID combination of VID[3:0]= 1111 (see Section 2.5), a system
can determine if a socket is occupied, and whether a processor core is present. See
the table below for states and values for determining the presence of a device.
D[63:0]#
I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data
path between the Intel Celeron processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
DBSY#
I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the Intel Celeron processor system bus to indicate that the data bus is in
use. The data bus is released after DBSY# is deasserted. This signal must connect
the appropriate pins on all Intel Celeron processor system bus agents.
DEFER#
I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all Intel Celeron processor system bus agents.
DRDY#
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multicycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all Intel Celeron processor system bus agents.
Table 59. Alphabetical Signal Reference (Sheet 2 of 7)
Signal
Type
Description
PGA370 Socket Occupation Truth Table
Signal
Value
Status
CPUPRES#
VID[3:0]
0
Anything other
than ‘1111’
Processor core installed in the PGA370
socket.
CPUPRES#
VID[3:0]
1
Any value
PGA370 socket not occupied.
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