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參數(shù)資料
| 型號： | BW1217X |
| 英文描述： | 16-bit bus buffer with 3-state outputs (non inverted) |
| 中文描述： | BW1217X 10位30MSPS模數(shù)轉(zhuǎn)換器BW1217X |數(shù)據(jù)資料 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | BW1217X |
BW1217X
10BIT 30MSPS ADC
SEC ASIC
ANALOG
FUNCTIONAL
DESCRIPTION
1.
BW1217X
comprising
multiplying
composed
multiplying
capacitors and two fully-differential amplifier.
is
a
three
4-bit
The
latching
is
step
flash
N-bit
A/D
ADC
flash
comparators,
of
Converter
and
ADC
three
DAC.
of
DAC
two
is
2
(n-1)
and
composed
2*(N+2)
2. BW1217X operates as follows. During the first
"L" cycle of external clock the analog input data
is tracked and sampled, and the input is held
from the rising edge of the external clock, which
is fed to the first 4-bit flash ADC, and the first
multiplying DAC. Multiplying DAC reconstructs
a voltage corresponding to the first 4-bit ADC's
output, and finally amplifies a residue voltage by
2
3
. The second 4-bit flash ADC, and MDAC are
worked as same manner, finally amplifiers a
residue voltage, which is the difference between
first MDAC's output and reconstructed voltage by
2
2
. The third 4-bit flash ADC, and MDAC are
worked as previous stages.
3. BW1217X has the error correction scheme,
which handles the output from mismatch in the
first, second and third flash ADC.
MAIN BLOCK DESCRIPTION
1. SAH
SAH(track and hold) is the circuit that samples
the analog input signal and holds that value until
next sample-time. It is good as small as its
different value between analog input signal and
output signal. SAH amp gain must be higher
than 66dB at least for less than 1/2LSB of SAH
error voltage at 10bit ADC and its conversion
frequency is 30MHz, its settling-time must be
shorten than 12ns. This SAH is consist of fully
differential op amp, switching tr. and sampling
capacitor.
The
sampling
non-overlapping
clocks(Q1,Q2)
capacitor value is 1.2pF. SAH uses independent
clock
and
are
sampling
bias to protect interruption of any other circuit.
SAH amp is designed that open-loop dc gain is
higher than 70dB, phase margin is higher than
60degree. Its input block is designed to be the
rail-to-rail
architecture
differential pair.
using
complementary
2. FLASH
The 4-bit flash converter compares analog
signal(SAH output) with reference voltage, and
that
result
transfers
to
correction
logic
block.
differential comparators of 15EA. Considering
self-offset, dynamic feed through error, it should
distinguish 40mV at least. First, the comparators
charge the reference voltage at the sampling
capacitors before transferred SAH output. Q2
works
this
process
and
sampling capacitors. That is, the comparators
compare
relative
different
voltage with dual reference voltage. Its output
during Q1 operation is stored at the pre-latch
block by Q1P.
MDAC
It
is
and
digital
fully
realized
Q1
discharges
this
values
dual
input
3. MDAC
MDAC is the most important block at this
ADC and it decides the characteristics. MDAC
is consist of amp1,amp2, selection logic and
capacitor array(c_array). C_array's compositions
are the capacitors to charge the analog input
and the reference voltage, Switches to control
the path. Selection logic controls the c_array
internal
switches.
If
output is all low, the switches of tsw1 are off,
the switches of tsw2 are all on. Therefore the
capacitors of c_array charges analog input values
held at SAH. If Q2 is high, it is reversed and
final MDAC output voltage is described the
following equation.
Q1
is
high,
selection's
Vout = (AIN - Vref)*8-Vref/2
AIN=AINT-1.5V
6 / 11
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