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參數(shù)資料
| 型號： | BUF12800 |
| 英文描述： | REFERENCE VOLTAGE GENERATOR for LCD GAMMA CORRECTION |
| 中文描述： | 參考電壓發(fā)生器，用于LCD伽瑪校正 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 282K |
| 代理商： | BUF12800 |
"#$%&''
SBOS315 DECEMBER 2004
www.ti.com
6
TWO-WIRE BUS OVERVIEW
The BUF12800 communicates through an industry-stan-
dard, two-wire interface to receive data in slave mode. This
standard uses a two-wire, open-drain interface that
supports multiple devices on a single bus. Bus lines are
driven to a logic low level only. The device that initiates the
communication is called a
master
, and the devices
controlled by the master are
slaves
. The master generates
the serial clock on the clock signal line (SCL), controls the
bus access, and generates the START and STOP
conditions.
To address a specific device, the master initiates a START
condition by pulling the data signal line (SDA) from a HIGH
to LOW logic level while SCL is HIGH. All slaves on the bus
shift in the slave address byte, with the last bit indicating
whether a read or write operation is intended. During the
ninth clock pulse, the slave being addressed responds to
the master by generating an Acknowledge and pulling
SDA LOW.
Data transfer is then initiated and 8 bits of data are sent
followed by an Acknowledge Bit. During data transfer,
SDA must remain stable while SCL is HIGH. Any change
in SDA while SCL is HIGH will be interpreted as a START
or STOP condition.
Once all data has been transferred, the master generates
a STOP condition indicated by pulling SDA from LOW to
HIGH while SCL is HIGH.
The BUF12800 can act only as a slave device; therefore,
it never drives SCL. SCL is an input only for the BUF12800.
ADDRESSING THE BUF12800
The address of the BUF12800 is 111010x, where
x
is the
state of the A0 pin. When the A0 pin is LOW, the device will
acknowledge on address 74h (1110100). If the A0 pin is
HIGH, the device will acknowledge on address 75h
(1110101).
Other valid addresses are possible through a simple mask
change. Contact your TI representative for information.
DATA RATES
The two-wire bus operates in one of three speed modes:
Standard: allows a clock frequency of up to 100kHz;
Fast: allows a clock frequency of up to 400kHz; and
High-speed mode (also called Hs mode): allows a
clock frequency of up to 3.4MHz.
The BUF12800 is fully compatible with all three modes. No
special action is required to use the device in Standard or
Fast modes, but High-speed mode must be activated. To
activate High-speed mode, send a special address byte of
00001xxx, with SCL = 400kHz, following the START
condition; where
xxx
are bits unique to the Hs-capable
master, which can be any value. The BUF12800 will
respond to the High-speed mode command regardless of
the value of these last three bits. This byte is called the Hs
master code. (Note that this is different from normal
address bytes—the low bit does not indicate read/write
status.) The BUF12800 will not acknowledge this byte; the
communication protocol prohibits acknowledgment of the
Hs master code. On receiving a master code, the
BUF12800 will switch on its Hs mode filters, and
communicate at up to 3.4MHz. Additional high-speed
transfers may be initiated without the Hs mode byte by
generating a repeat START without a STOP. The
BUF12800 will switch out of Hs mode at the first occurence
of a STOP condition.
GENERAL CALL RESET AND POWER-UP
The BUF12800 responds to a General Call Reset, which
is an address byte of 00h (0000 0000) followed by a data
byte of 06h (0000 0110). The BUF12800 acknowledges
both bytes. Upon receiving a General Call Reset, the
BUF12800 performs a full internal reset, as though it had
been powered off and then on. It always acknowledges the
General Call address byte of 00h (0000 0000), but does
not acknowledge any General Call data bytes other than
06h (0000 0110).
When the BUF12800 powers up, it automatically performs
a reset. As part of the reset, the BUF12800 is configured
based on the codes shown in Table 1.
Table 1. BUF12800 Reset Codes
RESET CODES
(Decimal)
992
864
800
768
704
576
448
320
256
224
160
32
BUFFER
BUFFER A
BUFFER B
BUFFER C
BUFFER D
BUFFER E
BUFFER F
BUFFER G
BUFFER H
BUFFER I
BUFFER J
BUFFER K
BUFFER L
(Hex)
Code 3E0
Code 360
Code 320
Code 300
Code 2C0
Code 240
Code 1C0
Code 140
Code 100
Code 0E0
Code 0A0
Code 020
(Binary)
11 1110 0000
11 0110 0000
11 0010 0000
11 0000 0000
10 1100 0000
10 0100 0000
01 1100 0000
01 0100 0000
01 0000 0000
00 1110 0000
00 1010 0000
00 0010 0000
Buffer values are calculated using Equation 1:
V
OUT
V
REFH
V
REFL
1024
decimal value of code
V
REFL
Other reset values are available as a custom
modification—contact your TI representative for details.
OUTPUT VOLTAGE
Buffer output values are determined by the reference
voltages (V
REFH
and V
REFL
) and the decimal value of the
binary input code used to program that buffer. The value is
calculated using Equation 1; see the
Reset and Power-Up
section. The valid voltage ranges for the reference
voltages are:
4V
V
REFH
V
S
0.2V and 0.2V
The BUF12800 outputs are capable of a full-scale voltage
output change in less than 4
μ
s—no intermediate steps are
required.
V
REFL
V
S
4V
(1)
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