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參數資料
| 型號： | BUF12800 |
| 英文描述： | REFERENCE VOLTAGE GENERATOR for LCD GAMMA CORRECTION |
| 中文描述： | 參考電壓發(fā)生器，用于LCD伽瑪校正 |
| 文件頁數： | 10/20頁 |
| 文件大?。?/td> | 282K |
| 代理商： | BUF12800 |
"#$%&''
SBOS315 DECEMBER 2004
www.ti.com
10
OUTPUT LATCH
Because the BUF12800 features a double-buffered
register structure, updating the DAC register is not the
same as updating the DAC output voltage. There are three
methods for latching transferred data from the storage
registers into the DACs to update the DAC output voltage.
Method 1 requires externally setting the latch pin low,
LD = LOW, which will update each DAC output voltage
whenever its corresponding register is updated.
Method 2 externally sets LD = HIGH to allow all DAC
output voltages to retain their values during data transfer
and until LD = LOW, which will simultaneously update the
output voltages of all 12 DACs to the new register values.
Method 3 uses software control. LD is maintained HIGH,
and all 12 DACs are updated when the master writes a 1
in bit 15 of any DAC register. The update will occur after
receiving the 16-bit data for the currently-written register.
Use methods 2 and 3 to transfer a future data set into the
first bank of registers in advance to prepare for a very fast
update of DAC output voltages.
The General Call Reset and the power-up reset will update
the DACs regardless of the state of the latch pin.
Table 2. BUF12800 Bus Address Options
BUF12800 ADDRESS
A0 Pin is LOW
(device will acknowledge on address 74h)
A0 Pin is HIGH
(device will acknowledge on address 75h)
ADDRESS
111 0100
111 0101
Table 3. Quick-Reference Table of DAC
Addresses
DAC
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC I
DAC J
DAC K
DAC L
ADDRESS
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
Table 4. Quick-Reference Table of Commands
COMMAND
General Call Reset
CODE
Address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110).
00001xxx, with SCL
≤
400kHz; where
xxx
are bits unique to the Hs-capable master.
This byte is called the Hs master code.
High-Speed Mode
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