參數(shù)資料
型號: BU7325HFV-TR
元件分類: XO, clock
英文描述: 78 MHz, OTHER CLOCK GENERATOR, PDSO6
封裝: ROHS COMPLIANT, HVSOF-6
文件頁數(shù): 6/21頁
文件大?。?/td> 1528K
代理商: BU7325HFV-TR
14/20
Block diagram, pin assignment/functions
BU3071HFV)
PIN NO.
PIN name
Function
1
VDD
Power supply
2
VSS
GND
3
OUT
Clock output terminal
4
OE
Output enable (L: disable, H: enable), equipped with Pull-down function, output fixed to L at disable
5
TEST
TEST pin, equipped with Pull-down function
6
IN
Clock input pin (28.6363 MHz input)
BU3072HFV)
PIN NO.
PIN name
Function
1
VDD
Power supply
2
VSS
GND
3
OUT
Clock output terminal (L:27.0000MHz, H:36.0000MHz)
4
PD
Power-down (L: Hi-Z, H: enable), equipped with Pull-down function, output set to Hi-Z at disable
5
SEL
Output selection (L: 27.0000 MHz, H: 36.0000 MHz)
6
IN
Clock input pin (48.0000 MHz input)
BU3073HFV)
PIN NO.
PIN name
Function
1
VDD
Power supply
2
VSS
GND
3
OUT
Clock output terminal (L:24.3750MHz, H:24.5454MHz)
4
PD
Power-down (L: disable, H: enable), equipped with Pull-down function, output set to L at disable
5
SEL
Output selection (L:24.3750MHz, H:24.5454MHz)
6
IN
Clock input pin (48.0000MHz input)
1:VDD
2:VSS
3:OUT
  6:
IN
  5:
TEST
  4:
OE
Fig.89
Fig.90
PLL
1/4
6pin:IN
4pin:OE
3pin:OUT
1:VDD
2:VSS
3:OUT
  6:
IN
  5:
SEL
  4:PD
Fig.92
Fig.91
PLL
1/4
6pin:IN
5pin:SEL
3pin:OUT
4pin:PD
DATA1
DATA2
1:VDD
2:VSS
3:OUT
  6:
IN
  5:
SEL
  4:PD
Fig.93
Fig.94
PLL
1/8
6pin:IN
5pin:SEL
3pin:OUT
4pin:PD
DATA1
DATA2
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