參數(shù)資料
型號(hào)： BU7325HFV-TR
元件分類： XO, clock
英文描述： 78 MHz, OTHER CLOCK GENERATOR, PDSO6
封裝： ROHS COMPLIANT, HVSOF-6
文件頁(yè)數(shù)： 16/21頁(yè)
文件大?。?/td> 1528K
代理商： BU7325HFV-TR
4/20
BU7322HFV（Ta=25℃, VDD=3.3V, Crystal frequency=27.0000MHz, unless otherwise specified.）
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
Output H voltage
VOH
2.8
-
V
IOH=-4.0mA
Output L voltage
VOL
-
0.5
V
IOL=4.0mA
Pull-down resistance
Rpd
25
50
100
kΩ
Pull-down resistance on input pin
Consumption current 1
IDD
-
10
13.5
mA
49.5MHz output, at no load
Consumption current 2
IDD2
-
9.5
13.0
mA
36.0MHz output, at no load
Standby current
IDDst
-
1
μ
A
OE=L
CLK_49.5
-
49.5000
-
MHz
SEL=L, IN*66/6/6
Output frequency
CLK_36
-
36.0000
-
MHz
SEL=H, IN*64/6/8
The following parameters represent design guaranteed performance.
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ
PJsSD
-
50
-
psec
※
1
Period-Jitter MIN-MAX
PJsABS
-
300
-
psec
※
2
Rise time
tr
-
2.5
-
nsec
Period of transition time required for the
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Fall time
tf
-
2.5
-
nsec
Period of transition time required for the
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time
tLOCK
-
200
usec
※
3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
BU7325HFV（Ta=25℃, VDD=3.3V, Crystal frequency=27.0000MHz, unless otherwise specified.）
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
Output H voltage
VOH
2.8
-
V
IOH=-4.0mA
Output L voltage
VOL
-
0.5
V
IOL=4.0mA
Pull-down resistance
Rpd
25
50
100
kΩ
Pull-down resistance on input pin
Consumption current 1
IDD1
-
11
15
mA
OE=H, SEL=L, at no load
Consumption current 2
IDD2
-
12
16.5
mA
OE=H, SEL=H, at no load
Standby current
IDDst
-
1
μ
A
OE=L
CLK_48
-
48.0000
-
MHz
SEL=L, IN*96/9/6
Output frequency
CLK_78
-
78.0000
-
MHz
SEL=H, IN*104/9/4
The following parameters represent design guaranteed performance.
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ
PJsSD
-
50
-
psec
※
1
Period-Jitter MIN-MAX
PJsABS
-
300
-
psec
※
2
Rise time
tr
-
1.5
-
nsec
Period of transition time required for the
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Fall time
tf
-
1.5
-
nsec
Period of transition time required for the
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time
tLOCK
-
200
usec
※
3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
Common to BU3071HFV, BU3072HFV, BU3073HFV, BU3076HFV, BU7322HFV, BU7325HFV
1
Period-Jitter 1σ
This parameter represents standard deviation (
=1σ) on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
2
Period-Jitter MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
3
Output Lock Time
This parameter represents elapsed time after power supply turns ON to reach a voltage of 3.0 V, after the system is switched from
Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency,
respectively.
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