參數(shù)資料
型號: BU4S71G2-TR
廠商: Rohm Semiconductor
文件頁數(shù): 11/14頁
文件大?。?/td> 0K
描述: IC GATE OR SINGLE 5SSOP
標(biāo)準(zhǔn)包裝: 3,000
系列: 4S
邏輯類型: 或門
電路數(shù): 1
輸入數(shù): 2
電源電壓: 3 V ~ 16 V
電流 - 靜態(tài)(最大值): 1µA
輸出電流高,低: 3.4mA,3.4mA
邏輯電平 - 低: 1.5 V ~ 4 V
邏輯電平 - 高: 3.5 V ~ 11 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 30ns @ 15V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 5-SSOP
封裝/外殼: 6-TFSOP(0.063",1.60mm 寬),5 引線
包裝: 帶卷 (TR)
1995 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX540
Lo
w
V
olta
g
e
Octal
Buff
er/Line
Driver
with
5V
T
olerant
Inputs
and
Outputs
AC Loading and Waveforms (Generic for LCX Family)
Figure 1. AC Test Circuit (CL includes probe and jig capacitance)
Waveform for Inverting and
Non-Inverting Functions
Propagation Delay, Pulse Width and
trec Waveforms
3-STATE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and
Recovery Time for Logic
trise and tfall
Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH, tPHZ
GND
VCC
DUT
CL
500
500
OPEN
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
GND
VI
TEST
SIGNAL
VCC
GND
DATA
IN
DATA
OUT
tpxx
Vmi
Vmo
VCC
GND
CONTROL
IN
CLOCK
OUTPUT
tPHL
tPLH
trec
tW
Vmi
Vmo
VCC
VX
VOL
GND
DATA
OUT
OUTPUT
CONTROL
tPZL
tPLZ
Vmi
Vmo
DATA
IN
CONTROL
INPUT
MR
OR
CLEAR
tS
tH
trec
VCC
GND
VCC
GND
Vmi
ANY
OUTPUT
tr
tf
VOH
VOL
10%
90%
Symbol
VCC
3.3V ± 0.3V
2.7V
2.5V ± 0.2V
Vmi
1.5V
VCC / 2
Vmo
1.5V
VCC / 2
Vx
VOL + 0.3V
VOL + 0.15V
Vy
VOH – 0.3V
VOH – 0.15V
DATA
OUT
OUTPUT
CONTROL
tPZH
tPHZ
VCC
GND
Vmi
VOH
VY
Vmo
74LCX540 Rev. 1.7.1
6
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