參數(shù)資料
型號(hào)： BU-65843F3-320
廠商： DATA DEVICE CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80
封裝： 0.880 INCH, CERAMIC, QFP-80
文件頁(yè)數(shù)： 31/75頁(yè)
文件大?。?/td> 532K
代理商： BU-65843F3-320
37
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
TABLE 57. ILLEGALIZATION TABLE MEMORY MAP
3FC
3BE
37D
3C2
381
33F
300
ADDRESS
Own Addr / Tx, SA 30, WC15-0
Own Addr / Rx, SA 31, MC15-0
Brdcst / Tx, SA 30, WC31-16
Own Addr / Tx, SA 1, WC15-0
Own Addr / Rx, SA 0, MC31-16
Brdcst / Rx, SA 0, MC15-0
DESCRIPTION
3FD
3BF
37E
3C3
382
340
301
Own Addr / Tx, SA 30, WC31-16
Own Addr / Rx, SA 31, MC31-16
Brdcst / Tx, SA 31, MC15-0
Own Addr / Tx, SA 1, WC31-16
Own Addr / Rx, SA 1, WC15-0
Brdcst / Tx, SA 0, MC31-16
Brdcst / SA 0, MC31-16
3FE
3C0
37F
383
341
302
Own Addr / Tx, SA 31, MC15-0
Own Addr / Tx, SA 0, MC15-0
Brdcst / Tx, SA 31, MC31-16
Own Addr / Rx, SA 1, WC31-15
Brdcst / Tx, SA 1,WC15-0
Brdcst / Rx, SA 1, WC15-0
3FF
3C1
380
342
303
Own Addr / Tx, SA 31, MC31-16
Own Addr / Tx, SA 0, MC31-16
Own Addr / Rx, SA 0, MC15-0
Brdcst / Tx, SA 1, WC31-16
Brdcst / Rx, SA 1, WC31-16
input by means of the RT ADDRESS (and PARITY) inputs, but
latched via host software; and (4) software programmable, by
means of an internal register. In all four configurations, the RT
address is readable by the host processor.
RT BUILT-IN-TEST (BIT) WORD
The bit map for the PCI Mini-ACE Mark3/Micro-ACE TE's inter-
nal RT Built-in-Test (BIT) Word is indicated in TABLE 58.
OTHER RT FEATURES
The PCI Mini-ACE Mark3/Micro-ACE TE includes options for the
Terminal flag status word bit to be set either under software con-
trol and/or automatically following a failure of the loopback self-
test. Other software programmable RT options include software
programmable RT status and RT BIT words, automatic clearing
of the Service Request bit following receipt of a Transmit vector
word mode command, options regarding Data Word transfers for
the Busy and Message error (illegal) Status word bits, and
options for the handling of 1553A and reserved mode codes.
MONITOR ARCHITECTURE
The PCI Mini-ACE Mark3/Micro-ACE TE includes three monitor
modes:
(1) A Word Monitor mode
(2) A selective message monitor mode
(3) A combined RT/message monitor mode
For new applications, it is recommended that the selective mes-
sage monitor mode be used, rather than the word monitor mode.
Besides providing monitor filtering based on RT address, T/R bit,
and subaddress, the message monitor eliminates the need to
determine the start and end of messages by software.
7F8
77C
6FA
784
702
67E
600
PCI BAR0 OFFSET
7FA
77E
6FC
786
704
680
602
7FC
780
6FE
706
682
604
7FE
782
700
684
606
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