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參數(shù)資料
| 型號： | BU-61705G4-170L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | CERAMIC, QFP-72 |
| 文件頁數(shù)： | 53/54頁 |
| 文件大?。?/td> | 576K |
| 代理商： | BU-61705G4-170L |
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Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
LOOPBACK TEST
The BU-61703/5 performs a loopback self-test at the end of each
non-broadcast message processed. The loopback test consists of
the following verifications: (1) The received version of every trans-
mitted word is verified for validity (encoding, bit count, parity) and
correct sync type; and (2) The received version of the last trans-
mitted word is verified by means of a bit-by-bit comparison to the
transmitted version of this word. If there is a transmitter timeout
(660.5 s) and/or if the loopback test fails for one or more trans-
mitted words, the Terminal flag status word bit will be set in
response to the next non-broadcast message.
Note that the setting of the Terminal flag status bit following a loop
test failure may be disabled by means of the Auto-Config feature;
i.e., by setting Auto-Config bit 4 to logic "0".
STATUS WORD
The Broadcast Command Received bit is formulated internally by
the SSRT. The Message Error Status bit will be set if the current
command is a Transmit Status Word or Transmit Last Command
mode command if there was an error in the data portion of the pre-
vious receive message. Message Error will also be set if ILLEGAL
has been sampled low by the SSRT for the current message. ILLE-
GAL, SRV_RQST, BUSY, and SSFLAG (Subsystem Flag) will be
sampled from their respective Status input pins approximately 2 s
following the mid-parity bit zero crossing of the received Command
Word. This time is 400 ns maximum following after the L_BRO,
T/R, SA4-0, and WC/MC/CWC4-0 outputs have been presented
valid.
PROTOCOL SELF-TEST
The SSRT includes a comprehensive, autonomous off-line self-
test of its internal protocol logic. The test includes a comprehen-
sive test of all registers, Manchester encoder and decoders, trans-
mitter failsafe timer, protocol logic, and the internal FIFO.
This test is completed in approximately 32,000 clock cycles. That
is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7 ms
at 12 MHz, and 3.2 ms at 10 MHz. While the SSRT is performing
its off-line self-test, it will ignore (and therefore not respond to) all
messages received from the 1553 bus.
Unless disabled by means of the SSRT's Auto-Config feature, the
protocol self-test will be performed following the SSRT's power
turn-on (i.e., when MSTCLR is released high). If the Auto-Config
feature is used and Auto-Config bit 5 is set to logic "0", then a fail-
ure of the protocol self-test following power turn-on will result in the
SSRT not going online. If bit 5 is set to logic "0" and the protocol
self-test passes following power turn-on, the SSRT will go online.
The protocol self-test will also be performed following receipt of an
Initiate self-test mode command from the 1553 bus. If an Initiate
self-test mode command is received by the SSRT, and Auto-
Config bit 5 is set to logic "0", then a failure of the protocol self-test
following will result in the SSRT going offline.
receive command word followed by the correct number of valid
data words and assuming that all words are successfully trans-
ferred to the subsystem, a negative pulse will be asserted on the
output Good Block Received (GBR). The width of this pulse is two
clock cycles.
RT-TO-RT TRANSFER ERRORS
For the case where the SSRT is the receiving RT of an RT-to-RT
transfer, if the transmitting RT does not respond within the speci-
fied time period, the SSRT will determine that a timeout condition
has occurred. The value of the SSRT's RT-to-RT timeout timer is in
the range from 17.5 to 18.5 s, and is specified from the mid-par-
ity bit crossing of the transmit command word to the mid-sync
crossing of the transmitting RT's status word. In the case of an RT-
to-RT timeout, the SSRT will not respond and the RT-to-RT NO
TRANSFER TIMEOUT bit (bit 2) of the SSRT's BIT Word will be
set to logic "1".
Also, if the SSRT is the receiving RT for an RT-to-RT transfer, and
the T/R bit of the second command word is logic "0", or the RT
address field for the transmit command is the same as for the
receive command, or the subaddress for the transmit command is
00000 or 11111, the BU-61703/5 will not respond, and will set the
RT-to-RT SECOND COMMAND ERROR bit (bit 1) of the RT BIT
word to logic "1".
RT STATUS, ERROR HANDLING, AND MESSAGE TIM-
ING SIGNALS
Message transfers and transfer errors are indicated by means of
the INCMD, HS_FAIL, MSG_ERR, and RTFAIL error indication
outputs. Additional error detection and indication mechanisms
include updating of the internal command, RT status and BIT word
registers.
The BU-61703/5 provides a number of timing signals during the
processing of 1553 messages. INCMD is asserted low when a
new command is received. At the end of a message (either valid
or invalid), INCMD transitions from low to high.
As discussed above, HS_FAIL will be asserted low if the subsys-
tem fails to respond to DTREQ within the maximum amount of
time (10 s).
Following the last data word transfer for a valid non-mode code
receive message (for either non-burst mode or burst mode), GBR
will be asserted low for two clock cycles.
MSG_ERR is asserted as a low output level following any detect-
ed error in a received message, except for an error in the com-
mand word. If an error is detected in a received command word,
the rest of the message will be ignored.
If MSG_ERR and/or HS_FAIL have been asserted (low), they will
be cleared to logic "1" following receipt of a subsequent valid com-
mand word.
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