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參數(shù)資料
| 型號(hào)： | BT458LPJ110 |
| 英文描述： | Video DAC with Color Palette (RAMDAC) |
| 中文描述： | 視頻DAC的調(diào)色板（的RAMDAC） |
| 文件頁數(shù)： | 12/60頁 |
| 文件大?。?/td> | 647K |
| 代理商： | BT458LPJ110 |
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1.0 Circuit Description
Bt457/Bt458
1.2 Pin Descriptions
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
1-4
Conexant
L45801 Rev. N
PLL
Phase lock loop current output
—
Bt457 only. This high-impedance current source is used to enable multiple
Bt457s to be synchronized with subpixel resolution when used with an external PLL. A logical 1 on the BLANK*
input results in no current being output onto this pin, while a logical 0 results in the following current being
output:
PLL (mA) = 3,227 * VREF (V) / RSET (
)
If subpixel synchronization of multiple devices is not required, this output should be connected to GND (either
directly or through a resistor up to 150
).
COMP
Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 μF ceramic
capacitor must be connected between this pin and VAA (
Figure 3-2
). Connecting the capacitor to VAA rather than
to GND provides the highest possible power supply noise rejection. The COMP capacitor must be as close to the
device as possible to keep lead lengths to an absolute minimum and to maximize the capacitor's self-resonant
frequency to be greater than the LD* frequency. The PC Board Layout Considerations section contains critical
layout criteria.
FSADJUST
Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the
full-scale video signal (
Figure 3-1
). The IRE relationships in
Figure 1-4
are maintained, regardless of the full-scale
output current.
The relationship between RSET and the full-scale output current on IOG (or IOUT for the Bt457) is as follows:
RSET (
) = 11,294 * VREF (V) / IOG (mA)
The full-scale output current on IOR and IOB (for the Bt458) for a given RSET is as follows:
IOR, IOB (mA) = 8,067 * VREF (V) / RSET (
)
VREF
Voltage reference input. An external voltage reference circuit, such as that illustrated in
Figure 3-2
, must supply
this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not
recommended, because any low-frequency power supply noise on VREF is directly coupled onto the analog
outputs. A 0.1 μF ceramic capacitor is used to decouple this input to VAA, as shown in
Figure 3-2
. If VAA is
excessively noisy, better performance can be obtained by decoupling VREF to GND. The decoupling capacitor
must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to the PC Board
Layout Considerations section for critical layout criteria.
CLOCK,
CLOCK*
Clock inputs. These differential clock inputs are driven by ECL logic configured for single-supply (+5 V)
operation. The clock rate is typically the pixel clock rate of the system. Refer to the PC Board Layout
Considerations section for critical layout criteria.
CE*
Chip enable control input (TTL compatible). This input must be a logical 0 to enable data to be written to or read
from the device. During write operations, data is internally latched on the rising edge of CE*. Glitches should be
avoided on this edge-triggered input.
R/W
Read/write control input (TTL compatible). To write data to the device, both CE* and R/W must be a logical 0. To
read data from the device, CE* must be a logical 0 and R/W must be a logical 1. R/W is latched on the falling edge
of CE*.
C[1,0]
Command control inputs (TTL compatible). C0 and C1 specify the type of read or write operation being
performed, as presented in
Table 1-3
. They are latched on the falling edge of CE*.
D[7:0]
Data bus (TTL compatible). Data transfers into and out of the device over this 8-bit bidirectional data bus. D0 is
the least significant bit.
VAA
Analog power. All VAA pins must be connected together on the same PCB plane to prevent latchup. Refer to the
PC Board Layout Considerations section for critical layout criteria.
GND
Analog ground. All GND pins must be connected together on the same PCB plane to prevent latchup. Refer to the
PC Board Layout Considerations section for critical layout criteria.
Table 1-1. Pin Descriptions
(2 of 2)
Pin Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BT458LPJ125 | Video DAC with Color Palette (RAMDAC) |
| BT458LPJ135 | Video DAC with Color Palette (RAMDAC) |
| BT458LPJ165 | Video DAC with Color Palette (RAMDAC) |
| BT458LPJ80 | Video DAC with Color Palette (RAMDAC) |
| BT457KG125 | Video DAC with Color Palette (RAMDAC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BT458LPJ125 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| BT458LPJ135 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| BT458LPJ165 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| BT458LPJ80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| BT471KPJ35-695 | 制造商:BT 功能描述: |
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