參數(shù)資料
型號(hào)： BT132SERIESD
英文描述： Triacs logic level
中文描述： 雙向可控硅邏輯電平
文件頁(yè)數(shù)： 1/6頁(yè)
文件大小： 40K
代理商： BT132SERIESD
Philips Semiconductors
Product specification
Triacs
logic level
BT132 series D
GENERAL DESCRIPTION
QUICK REFERENCE DATA
Glass
triacs in a plastic envelope, intended
for
use
in
general
bidirectional switching and phase
control applications. These devices
are intended to be interfaced directly
to microcontrollers, logic integrated
circuits and other low power gate
trigger circuits.
passivated,
sensitive
gate
SYMBOL
PARAMETER
MAX.
MAX. UNIT
purpose
BT132-
500D
500
1
16
600D
600
1
16
V
DRM
I
T(RMS)
I
TSM
Repetitive peak off-state voltages
RMS on-state current
Non-repetitive peak on-state current
V
A
A
PINNING - TO92
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
main terminal 2
2
gate
3
main terminal 1
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
-500
500
1
-600
600
1
V
DRM
Repetitive peak off-state
voltages
RMS on-state current
Non-repetitive peak
on-state current
-
V
I
T(RMS)
I
TSM
full sine wave; T
lead
≤
51 C
full sine wave; T
j
surge
t = 20 ms
t = 16.7 ms
t = 10 ms
I
TM
= 1.5 A; I
= 0.2 A;
dI
G
/dt = 0.2 A/
μ
s
-
1
A
-
-
-
16
17.6
1.28
A
A
I
2
t
dI
T
/dt
I
2
t for fusing
Repetitive rate of rise of
on-state current after
triggering
A
2
s
T2+ G+
T2+ G-
T2- G-
T2- G+
-
-
-
-
-
-
-
-
50
50
50
10
2
5
5
0.5
150
125
A/
μ
s
A/
μ
s
A/
μ
s
A/
μ
s
A
V
W
W
C
C
I
GM
V
GM
P
GM
P
G(AV)
T
stg
T
j
Peak gate current
Peak gate voltage
Peak gate power
Average gate power
Storage temperature
Operating junction
temperature
over any 20 ms period
-40
-
T1
T2
G
3 2 1
1
Although not recommended, off-state voltages up to 800V may be applied without damage, but the triac may
switch to the on-state. The rate of rise of current should not exceed 3 A/
μ
s.
January 1998
1
Rev 1.000
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
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BT134_SERIES_D 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Triacs logic level
BT134_SERIES_E 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Triacs sensitive gate
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