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參數(shù)資料
| 型號(hào)： | BSP127 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | N-channel enhancement mode vertical D-MOS transistor |
| 中文描述： | 0.35 A, 270 V, 8 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 50K |
| 代理商： | BSP127 |
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP127
CHARACTERISTICS
T
j
= 25
°
C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
6.5
9
400
55
20
5
MAX. UNIT
1
100
2
8
14
80
30
10
V
(BR)DSS
I
DSS
±
I
GSS
V
GS(th)
R
DS(on)
drain-source breakdown voltage
drain-source leakage current
gate-source leakage current
gate-source threshold voltage
drain-source on-resistance
I
D
= 10
μ
A; V
GS
= 0
V
DS
= 220 V; V
GS
= 0
±
V
GS
= 20 V; V
DS
= 0
I
D
= 1 mA; V
GS
= V
DS
I
D
= 250 mA; V
GS
= 10 V
I
D
= 20 mA; V
GS
= 2.4 V
I
D
= 250 mA; V
DS
= 25 V
V
DS
= 25 V; V
GS
= 0; f = 1 MHz
V
DS
= 25 V; V
GS
= 0; f = 1 MHz
V
DS
= 25 V; V
GS
= 0; f = 1 MHz
270
0.8
200
V
μ
A
nA
V
mS
pF
pF
pF
Y
fs
C
iss
C
oss
C
rss
transfer admittance
input capacitance
output capacitance
feedback capacitance
Switching times (see Figs
2
and
3
)
t
on
turn-on time
I
D
= 250 mA; V
DD
= 50 V;
V
GS
= 0 to 10 V
I
D
= 250 mA; V
DD
= 50 V;
V
GS
= 0 to 10 V
5
10
ns
t
off
turn-off time
20
30
ns
Fig.2 Switching times test circuit.
V
DD
= 50 V.
handbook, halfpage
MBB691
50
VDD = 50 V
ID
10 V
0 V
Fig.3 Input and output waveforms.
handbook, halfpage
MBB692
10 %
90 %
90 %
10 %
ton
toff
OUTPUT
INPUT
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