參數(shù)資料
型號： BS62LV2006STIG55
廠商： BRILLIANCE SEMICONDUCTOR, INC.
英文描述： Very Low Power/Voltage CMOS SRAM 256K X 8 bit
中文描述： 非常低功率/電壓CMOS SRAM的256K × 8位
文件頁數(shù)： 6/9頁
文件大?。?/td> 321K
代理商： BS62LV2006STIG55
R0201-BS62LV2006
Revision 1.1
Jan.
2004
6
BSI
BS62LV2006
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WR1
t WC
(3)
t CW
(11)
t CW
(2)
t WP
t AW
t OHZ
(4,10)
t AS
t WR2
(3)
t DH
t DW
D
IN
D
OUT
WE
CE2
CE1
OE
ADDRESS
(5)
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
(Vcc = 3.0~5.5V)
(Vcc = 2.7~5.5V)
UNIT
t
AVAX
t
WC
Write Cycle Time
55
--
70
--
ns
t
E1LWH
t
CW
Chip Select to End of Write
55
--
70
--
ns
t
AVWL
t
AS
Address Setup Time
0
--
0
--
ns
t
AVWH
t
AW
Address Valid to End of Write
55
--
70
--
ns
t
WLWH
t
WP
Write Pulse Width
30
--
35
--
ns
t
WHAX
t
WR1
Write recovery Time
(CE1,WE)
0
--
0
--
ns
t
E2LAX
t
WR2
(CE2)
0
--
0
--
ns
t
WLQZ
t
WHZ
Write to Output in High Z
--
25
--
30
ns
t
DVWH
t
DW
Data to Write Time Overlap
25
--
30
--
ns
t
WHDX
t
DH
Data Hold from Write Time
0
--
0
--
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
--
25
--
30
ns
t
WHOX
t
OW
End of Write to Output Active
5
--
5
--
ns
MIN. TYP. MAX.
Write recovery Time
CYCLE TIME : 55ns
CYCLE TIME : 70ns
相關(guān)PDF資料
PDF描述
BS62LV2006STIP55 Very Low Power/Voltage CMOS SRAM 256K X 8 bit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BS62LV2006STIG70 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power CMOS SRAM 256K X 8 bit
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