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參數(shù)資料
| 型號(hào)： | BQ4847Y |
| 英文描述： | Fast Recovery Glass Passivated Rectifier Diodes |
| 中文描述： | 時(shí)鐘模塊CPU監(jiān)控 |
| 文件頁(yè)數(shù)： | 13/20頁(yè) |
| 文件大小： | 1155K |
| 代理商： | BQ4847Y |
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13
Read Cycle
(TA= TOPR, VCCmin
≤
VCC
≤
VCCmax)
Symbol
Parameter
Min.
Max.
Unit
Conditions
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Read cycle time
70
-
ns
Address access time
-
70
ns
Output load A
Chip select access time
-
70
ns
Output load A
Output enable to output valid
-
35
ns
Output load A
Chip select to output in low Z
5
-
ns
Output load B
Output enable to output in low Z
0
-
ns
Output load B
Chip deselect to output in high Z
0
25
ns
Output load B
Output disable to output in high Z
0
25
ns
Output load B
Output hold from address change
10
-
ns
Output load A
Write Cycle
(TA=TOPR , VCCmin
≤
VCC
≤
VCCmax)
Symbol
t
WC
t
CW
t
AW
Parameter
Min.
70
65
65
Max.
-
-
-
Unit
ns
ns
ns
Conditions
Write cycle time
Chip select to end of write
Address valid to end of write
(1)
(1)
t
AS
Address setup time
0
-
ns
Measured from address valid to beginning
of write. (2)
Measured from beginning of write to end of
write. (1)
Measured from WE going high to end of
write cycle. (3)
Measured from CS going high to end of
write cycle. (3)
Measured to first low-to-high transition of
either CS or WE.
Measured from WE going high to end of
write cycle. (4)
Measured from CS going high to end of
write cycle. (4)
I/O pins are in output state. (5)
I/O pins are in output state. (5)
t
WP
Writepulsewidth
55
-
ns
t
WR1
Writerecovery time(writecycle1)
5
-
ns
t
WR2
Writerecovery time(writecycle2)
15
-
ns
t
DW
Data valid toend of write
30
-
ns
t
DH1
Data hold time(writecycle1)
0
-
ns
t
DH2
Data hold time(writecycle2)
10
-
ns
t
WZ
t
OW
Write enabled to output in high Z
Output active from end of write
0
0
25
-
ns
ns
Notes:
1.
A write ends at the earlier transition of CS going high and WE going high.
2.
A write occurs during the overlap of a low CS and a low WE. A write begins at the later transition
of CS going low and WE going low.
3.
Either t
WR1
or t
WR2
must be met.
4.
Either t
DH1
or t
DH2
must be met.
5.
If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Aug. 1995
bq4845/bq4845Y
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