參數(shù)資料
型號(hào)： BQ4802LYDWR
廠商： TEXAS INSTRUMENTS INC
元件分類： XO, clock
英文描述： 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝： GREEN, PLASTIC, SOIC-28
文件頁(yè)數(shù)： 5/24頁(yè)
文件大?。?/td> 481K
代理商： BQ4802LYDWR
bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
www.ti.com
13
Table 3. Clock and Control Register Map
BIT
DESCRIPTION
24/12
24- or 12-hour data representation
ABE
Alarm interrupt enable in battery-backup mode
AF
Alarm interrupt flag
AIE
Alarm interrupt enable
ALM0–ALM1
Alarm mask bits
BVF
Battery-valid flag
DSE
Daylight savings enable
PF
Periodic interrupt flag
PIE
Periodic interrupt enable
PM/AM
PM or AM indication
PWRF
Power-fail interrupt flag
PWRIE
Power-fail interrupt enable
RS0–RS3
Periodic interrupt rate
STOP
Oscillator stop and start
UTI
Update transfer inhibit
WD0–WD2
Watchdog time-out rate
CLOCK MEMORY INTERFACE
The bq4802Y/bq4802LY has the same interface for
clock/calendar and control information as standard
SRAM. To read and write to these locations, the user must
put the bq4802Y/bq4802LY in the proper mode and meet
the timing requirements.
READ MODE
The bq4802Y/bq4802LY is in read mode whenever OE
(output enable) is low and CS (chip select) is low. The
unique address, specified by the four address inputs,
defines which one of the 16 clock/calendar bytes is to be
accessed. The bq4802Y/bq4802LY makes valid data
available at the data I/O pins within tAA (address access
time). This occurs after the last address input signal is
stable, and providing the CS and OE (output enable)
access times are met. If the CS and OE access times are
not met, valid data is available after the latter of chip select
access time (tACS) or output enable access time (tOE).
CS and OE control the state of the eight three-state data
I/O signals. If the outputs are activated before tAA, the data
lines are driven to an indeterminate state until tAA. If the
address inputs are changed while CS and OE remain low,
output data remains valid for tOH (output data hold time),
but goes indeterminate until the next address access.
WRITE MODE
The bq4802Y/bq4802LY is in write mode whenever WE
and CS are active. The start of a write is referenced from
the latter-occurring falling edge of WE or CS. A write is
terminated by the earlier rising edge of WE or CS. The
addresses must be held valid throughout the cycle. CS or
WE must return high for a minimum of tWR2 from CS or
tWR1 from WE prior to the initiation of another read or write
cycle.
Data-in must be valid tDW prior to the end of write and
remain valid for tDH1 or tDH2 afterward. OE should be kept
high during write cycles to avoid bus contention; although,
if the output bus has been activated by a low on CS and
OE, a low on WE disables the outputs tWZ after WE falls.
READING THE CLOCK
Once every second, the user-accessible clock/calendar
locations are updated simultaneously from the internal
real-time counters. To prevent reading data in transition,
updates to the bq4802Y/bq4802LY clock registers should
be halted. Updating is halted by setting the update transfer
inhibit (UTI) bit D3 of the control register E. As long as the
UTI bit is 1, updates to user-accessible clock locations are
inhibited. Once the frozen clock information is retrieved by
reading the appropriate clock memory locations, the UTI
bit should be reset to 0 in order to allow updates to occur
from the internal counters. Because the internal counters
are not halted by setting the UTI bit, reading the clock
locations has no effect on clock accuracy. Once the UTI bit
is reset to 0, the internal registers update within one
second the user-accessible registers with the correct time.
A halt command issued during a clock update allows the
update to occur before freezing the data.
SETTING THE CLOCK
The
UTI
bit
must
also
be
used
to
set
the
bq4802Y/bq4802LY clock. Once set, the locations can be
written with the desired information in BCD format.
Resetting the UTI bit to 0 causes the written values to be
transferred to the internal clock counters and allows
updates to the user-accessible registers to resume within
one second.
STOPPING AND STARTING THE CLOCK
OSCILLATOR
The bq4802Y/bq4802LY clock can be programmed to turn
off when the part goes into battery back-up mode by setting
STOP to 0 prior to power down. If the board using the
bq4802Y/bq4802LY is to spend a significant period of time
in storage, the STOP bit can be used to preserve some
battery capacity. STOP set to 1 keeps the clock running
when VCC drops below VSO. With VCC greater than VSO,
the bq4802Y/bq4802LY clock runs regardless of the state
of STOP.
POWER-DOWN/POWER-UP CYCLE
The bq4802Y/bq4802LY continuously monitors VCC for
out-of-tolerance. During a power failure, when VCC falls
below VPFD, the bq4802Y/bq4802LY write-protects the
clock and storage registers. The power source is switched
to BC when VCC is less than VPFD and BC is greater than
VPFD, or when VCC is less than VBC and VBC is less than
相關(guān)PDF資料
PDF描述
BU-61743F3-292Z 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-362Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-420Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-450L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-472Z 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BQ4802LYDWRG4 功能描述:實(shí)時(shí)時(shí)鐘 Parallel RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
BQ4802LYPW 功能描述:實(shí)時(shí)時(shí)鐘 Parallel RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
BQ4802LYPWG4 功能描述:實(shí)時(shí)時(shí)鐘 Parallel RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
BQ4802LYPWR 功能描述:實(shí)時(shí)時(shí)鐘 Parallel RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
BQ4802LYPWRG4 功能描述:實(shí)時(shí)時(shí)鐘 Parallel RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
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