參數(shù)資料
型號: BQ4802LYDWR
廠商: TEXAS INSTRUMENTS INC
元件分類: XO, clock
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: GREEN, PLASTIC, SOIC-28
文件頁數(shù): 24/24頁
文件大?。?/td> 481K
代理商: BQ4802LYDWR
bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
www.ti.com
9
WRITE CYCLE (TA = TOPR, VCC = 5 V)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tWC
Write cycle time
200
ns
tCW
Chip select to end of write
See Note 1
195
ns
tAW
Address valid to end of write
See Note 1
195
ns
tAS
Address setup time
Measured from address valid to beginning of write(2)
30
ns
tWP
Write pulse width
Measured from beginning of write to end of write(1)
165
ns
tWR1
Write recovery time (write cycle 1)
Measured from WE going high to end of write cycle(3)
5
ns
tWR2
Write recovery time (write cycle 2)
Measured from CS going high to end of write cycle(3)
15
ns
tDW
Data valid to end of write
Measured to first low-to-high transition of either CS or WE
50
ns
tDH1
Data hold time (write cycle 1)
Measured from WE going high to end of write cycle(4)
0
ns
tDH2
Data hold time (write cycle 2)
Measured from CS going high to end of write cycle(4)
10
ns
tWZ
Write enable to output high Z
I/O pins are in output state.(5)
0
45
ns
tOW
Output active from end of write
I/O pins are in output state.(5)
0
ns
(1) A write cycle ends at the earlier transition of CS going high and WE going high.
(2) A write occurs during the overlap of a low CS and a low WE. A write cycle begins at the later transition of CS going low or WE going low.
(3) Either tWR1 or tWR2 must be met.
(4) Either tDH1 or tDH2 must be met.
(5) If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high Z state.
WRITE CYCLE (TA = TOPR, VCC = 3.3 V)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tWC
Write cycle time
300
ns
tCW
Chip select to end of write
See Note 1
250
ns
tAW
Address valid to end of write
See Note 1
250
ns
tAS
Address setup time
Measured from address valid to beginning of write(2)
56
ns
tWP
Write pulse width
Measured from beginning of write to end of write(1)
280
ns
tWR1
Write recovery time (write cycle 1)
Measured from WE going high to end of write cycle(3)
8
ns
tWR2
Write recovery time (write cycle 2)
Measured from CS going high to end of write cycle(3)
25
ns
tDW
Data valid to end of write
Measured to first low-to-high transition of either CS or WE
80
ns
tDH1
Data hold time (write cycle 1)
Measured from WE going high to end of write cycle(4)
0
ns
tDH2
Data hold time (write cycle 2)
Measured from CS going high to end of write cycle(4)
15
ns
tWZ
Write enable to output high Z
I/O pins are in output state.(5)
0
60
ns
tOW
Output active from end of write
I/O pins are in output state.(5)
0
ns
(1) A write cycle ends at the earlier transition of CS going high and WE going high.
(2) A write occurs during the overlap of a low CS and a low WE. A write cycle begins at the later transition of CS going low or WE going low.
(3) Either tWR1 or tWR2 must be met.
(4) Either tDH1 or tDH2 must be met.
(5) If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high Z state.
相關(guān)PDF資料
PDF描述
BU-61743F3-292Z 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-362Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-420Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-450L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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