參數(shù)資料
型號: BQ4015YMB-120N
英文描述: Avalanche Bridge Rectifiers
中文描述: NVRAM中(基于電池)
文件頁數(shù): 9/13頁
文件大小: 450K
代理商: BQ4015YMB-120N
9
bq4013/Y
Power-Down/Power-Up Cycle
(TA= TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
t
PF
V
CC
slew, 4.75 to 4.25 V
300
-
-
μ
s
t
FS
V
CC
slew, 4.25 to V
SO
10
-
-
μ
s
t
PU
V
CC
slew, V
SO
to V
PFD
(max.)
0
-
-
μ
s
t
CER
Chip enable recovery time
40
80
120
ms
Time during which
SRAM is
write-protected after
V
CC
passes V
PFD
on
power-up.
t
DR
Data-retention time in
absence of V
CC
10
-
-
years
T
A
= 25°C. (2)
t
DR-N
Data-retention time in
absence of V
CC
6
-
-
years
T
A
= 25°C (2); industrial
temperature range only
t
WPT
Write-protect time
40
100
150
μ
s
Delay after V
CC
slews
down past V
PFD
before
SRAM is
write-protected.
Notes:
1.
Typical values indicate operation at T
A
= 25°C, V
CC
= 5V.
2.
Battery is disconnected from circuit until after V
CC
is applied for the first time. t
DR
is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution:
Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
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