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參數(shù)資料
| 型號： | BQ3285LQ |
| 英文描述： | Real-Time Clock |
| 中文描述： | 實時時鐘 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 831K |
| 代理商： | BQ3285LQ |
DS
Data strobe input
When MOT = V
CC
, DS controls data trans-
fer during a bq3285EC/LC bus cycle. Dur-
ing a read cycle, the bq3285EC/LC drives
the bus after the rising edge on DS. During
a write cycle, the falling edge on DS is used
tolatch writedata intothechip.
When MOT = V
SS
, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
R /W
R ead/write input
When MOT = V
CC
, the level on R/W identi-
fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
When MOT = V
SS
, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel-
based system.
The rising edge on R/W
latches data intothebq3285EC/LC.
CS
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cleaccessing thebq3285EC/LC.
INT
Interrupt request output
INT is an open-drain output.
alarm INT to be valid in battery-backup
mode. To use this feature, connect INT
through a resistor to a power supply other
than V
CC
. INT is asserted low when any
event flag is set and the corresponding
event enable bit is also set. INT becomes
high-impedance whenever register C is read
(seetheControl/Status Registers section).
This allows
32K
32.768 kHz output
32K provides a buffered 32.768 kHz output.
The frequency remains on and fixed at
32.768kHz as long as V
CC
is valid.
E XT R AM
E xtended R AM enable
Enables 128 bytes of additional nonvolatile
SRAM. It is connected internally to a 30k
pull-down resistor. To access the RTC regis-
ters, EXTRAM must below.
R CL
R AM clear input
A low level on the RCL pin causes the con-
tents of each of the 242 storage bytes to be
set to FF(hex).
The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of V
CC
. Us-
ing RAM clear does not affect the battery
load. This pin is connected internally to a
30k
pull-up resistor.
BC
3V backup cell input
BC should be connected to a 3V backup cell
for RTC operation and storage register non-
volatility in the absence of system power.
When V
CC
slews down past V
BC
(3V typi-
cal), the integral control circuitry switches
the power source to BC. When V
CC
returns
above V
BC
, the power source is switched to
V
CC
.
Upon power-up, a voltage within the V
BC
range must be present on the BC pin for
theoscillator tostart up.
R ST
R eset input
The bq3285E C/L C is reset when RST is
pulled low. When reset, INT becomes high
impedance, and the bq3285EC/LC is not ac-
cessible. Table 4 in the Control/Status Reg-
isters section lists the register bits that are
cleared by a reset.
Reset may be disabled by connecting RST
to V
CC
. This allows the control bits to re-
tain
their
states
down/power-up cycles.
through
power-
X1–X2
Crystal inputs
The X1–X2 inputs are provided for an ex-
ternal 32.768kHz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci-
tance. A trimming capacitor may be neces-
sary for extremely precise time-base gen-
eration.
In the absence of a crystal, a 32.768kHz
waveform can befed intotheX1 input.
3
bq3285EC/LC
July 1996
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| BQ3285LS | Real-Time Clock |
| BQ3285LSS-N | Avalanche Glass Passivated Bridge Rectifiers |
| BQ3287AMT | Avalanche Glass Passivated Bridge Rectifiers |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BQ3285LQ- | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Real-Time Clock RTC |
| BQ3285LQN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Real-Time Clock RTC |
| BQ3285LS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| BQ3285LS- | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Real-Time Clock RTC |
| BQ3285LSN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Real-Time Clock RTC |
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