參數(shù)資料
型號: BH16823ADGG
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 18-bit bus interface D-type flip-flop with reset and enable 3-State
中文描述: ABT SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝: 6.10 MM, PLASTIC, SOT-364-1, TSSOP2-56
文件頁數(shù): 6/12頁
文件大小: 86K
代理商: BH16823ADGG
Philips Semiconductors
Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
1998 Feb 27
6
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
°
C
T
amb
= –40
°
C
to +85
°
C
UNIT
MIN
TYP
MAX
MIN
MAX
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
–0.9
–1.2
–1.2
V
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
2.5
2.9
2.5
V
V
OH
High-level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
3.0
3.4
3.0
V
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
2.0
2.4
2.0
V
V
OL
Low-level output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
V
RST
Power-up output low
voltage
3
V
CC
= 5.5V; I
OL
= 1mA; V
I
= GND or V
CC
0.13
0.55
0.55
V
I
I
Input leakage curent
In ut leakage curent
= 5.5V; V
= V
V
CC
5.5V V
I
V
CC
or GND
±
0.01
±
1
±
1
μ
A
Input leakage current
In ut leakage current
74ABTH16823A
V
CC
= 5.5V; V
I
= V
CC
or GND
Control
pins
±
0.01
±
1
±
1
μ
A
I
I
V
CC
= 5.5V; V
I
= V
CC
Data pins
0.01
1
1
μ
A
V
CC
= 5.5V; V
I
= 0
–2
–3
–5
μ
A
V
CC
= 4.5V; V
I
= 0.8V
35
35
I
HOLD
Bus Hold current inputs
5
74ABTH16823A
V
CC
= 4.5V; V
I
= 2.0V
–75
–75
μ
A
V
CC
= 5.5V; V
I
= 0 to 5.5V
±
800
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
V
CC
= 2.1V; V
O
= 0.5V; V
I
= GND or V
CC
,
V
OE
= Don’t care
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
±
5.0
±
100
±
100
μ
A
I
PU/PD
Power-up/down 3-State
output current
4
±
5.0
±
50
±
50
μ
A
I
OZH
3-State output High current
1.0
10
10
μ
A
I
OZL
3-State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
–1.0
–10
–10
μ
A
I
CEX
Output High leakage
current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
50
50
50
μ
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
–50
–80
–180
–50
–180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or
V
CC
0.5
1
1
mA
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
9.0
19
19
mA
I
CCZ
V
CC
= 5.5V; Outputs 3–State;
V
I
CC
0.5
1
1
mA
I
CC
Additional supply current
per input pin
2
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.2
1
1
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
between 0V and 2.1V with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
±
10% a
transition time of up to 100
μ
sec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
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