參數(shù)資料
型號(hào)： BH161543DL
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 16-bit latched transceiver with dual enable and master reset 3-State
中文描述： ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝： PLASTIC, SSOP3-56
文件頁數(shù)： 2/12頁
文件大?。?/td> 85K
代理商： BH161543DL
Philips Semiconductors
Product specification
74ABT161543
74ABTH161543
16-bit latched transceiver with dual enable
and master reset (3-State)
2
1998 Feb 27
853-1798 19026
FEATURES
Two 8-bit octal transceivers with D-type latch
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
Multiple V
CC
and GND pins minimize switching noise
Back-to-back registers for storage
Separate controls for data flow in each direction
74ABTH161543 incorporates Bus hold data inputs which eliminate
the need for external pull-up resistors to hold unused inputs
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Same function as ABT16543 except for additional Master Reset
control pins
QUICK REFERENCE DATA
DESCRIPTION
The 74ABT161543 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT161543 16-bit registered transceiver contains two sets
of D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (nLEAB, nLEBA) and Output
Enable (nOEAB, nOEBA) inputs are provided for each register to
permit independent control of data transfer in either direction. Master
reset (MR) clears all registers simultaneously and sets them Low.
The outputs are guaranteed to sink 64mA.
Two options are available, 74ABT161543 which does not have the
Bus hold feature and 74ABTH161543 which inorporates the Bus
hold feature.
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
I
CCL
Propagation delay
nAx to nBx
Input capacitance
I/O capacitance
C
L
= 50pF; V
CC
= 5V
2.5
2.2
3
7
500
9
ns
V
I
= 0V or V
CC
V
O
= 0V or V
CC;
3-State
Outputs disabled; V
CC
= 5.5V
Outputs low; V
CC
= 5.5V
pF
pF
μ
A
mA
Quiescent supply current
ORDERING INFORMATION
PACKAGES
56-pin plastic SSOP Type III
56-pin plastic TSSOP Type II
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
ORDER CODE
BT161543DL
BT161543DGG
DRAWING NUMBER
SOT371-1
SOT364-1
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74ABT161543 DL
74ABT161543 DGG
74ABTH161543 DL
74ABTH161543 DGG
NORTH AMERICA
BT161543 DL
BT161543 DGG
BH161543 DL
BH161543 DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40,38, 37, 36, 34, 33
1, 56
28, 29
3, 54
26, 31
2, 55
27, 30
4, 25
11, 18, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1A0 – 1A7,
2A0 – 2A7
1B0 – 1B7,
2B0 – 2B7
1OEAB, 1OEBA,
2OEAB, 2OEBA
1EAB, 1EBA,
2EAB, 2EBA
1LEAB, 1LEBA,
2LEAB, 2LEBA
MRab, MRba
GND
V
CC
NAME AND FUNCTION
Data inputs/outputs
Data inputs/outputs
A to B / B to A Output Enable inputs (active-Low)
A to B / B to A Enable inputs (active-Low)
A to B / B to A Latch Enable inputs (active-Low)
Master reset
Ground (0V)
Positive supply voltage
相關(guān)PDF資料
PDF描述
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