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參數(shù)資料
| 型號： | AX88658AB |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | 8-Port 10/100/1000BASE-T Ethernet Switch |
| 中文描述： | 8端口10/100/1000BASE-T以太網(wǎng)交換機(jī) |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 343K |
| 代理商： | AX88658AB |
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ASIX ELECTRONICS CORPORATION
8
AX88658AB 8-Port 10/100/1000BASE-T Ethernet Switch
CONFIDENTIAL
2.0 I/O Definition
The following terms describe the AX88658A pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I
Input
O
Output
I/O
Input/Output
OD
Open Drain
2.1 RGMII/GMII/MII Interface
2.1.1 RGMII/GMII/MII Interface Port 0
Signal Name
I/O
GTX_CLK0
O
PU
PD
P
ODBI
Pull Up
Pull Down
Power Pin
Open drain with BI-direction
Pin No.
Y2
Description
125MHz Clock Output:
it is a continuous 125 MHz clock output to
giga-PHY operating at 1000BASE-T. That is, it is a timing reference for
TX_EN0 and TXD0[7:0]
Transmit Enable:
When TX_EN0 is asserted, data on TXD0[7:0] are
transmitted onto PHY. TX_EN0 is synchronous to GTX_CLK0 in
1000BASE-T mode and synchronous to TX_CLK0 in 10/100BASE-T
mode.
Transmit Data:
Synchronous to the rising of GTX_CLK0 in
1000BASE-T mode. And synchronous to rising edge of TX_CLK0 in
10/100BASE-T mode., For RGMII, only TXD0[3:0]
MII Transmit Clock Input:
TX_EN0 and TXD0[3:0] are
synchronous to the rising edge of this clock in 10/100BASE-T mode.
Collision Detect:
Active high to indicate that there is collision occurred
in half duplex mode. In full duplex mode COL0 is always low.
Carrier Sense:
Active high if there is carrier on medium. In half duplex
mode CRS0 is also asserted during transmission and asynchronous to
any clock.
Receive Data Valid:
Active high to indicate that data presented on
RXD0[7:0] is valid and synchronous to RX_CLK0.
Receive Clock Input:
125, 25 and 2.5 MHz is running at 1000/100/10
BASE-T mode respectively. RX_DV0 and RXD0[7:0] are
synchronous to rising edge of this clock.
Receive Data:
Data received by the PHY are presented on RXD0 and
synchronous
to
RX_CLK0.
10/100/1000BASE-T and RXD[7:4] is valid only in 1000BASE-T
modes. For RGMII, only RXD0[3:0]
TX_EN0
O
Y1
TXD0[7:0]
O
W1, V2, V1,
U3, U2,U1 ,
T2, T1
W5
TX_CLK0
I/PD
COL0
I/PD
Y5
CRS0
I/PD
U6
RX_DV0
I
U5
RX_CLK0
I
V5
RXD0[7:0]
I/PD
U4, V4, W4,
Y4, V3, W3,
Y3, W2
RXD0[3:0]
is
valid
in
2.1.2 RGMII/GMII/MII Interface Port 1
Signal Name
I/O
GTX_CLK1
O
TX_EN1
TXD1[7:0]
Pin No.
Y9
Description
125MHz Clock Output:
Please references section 2.1.1.
O
V8
Transmit Enable:
Please references section 2.1.1.
O
W8, Y8,
V7, W7, Y7,
V6, W6, Y6
U11
Transmit Data:
Please references section 2.1.1.
TX_CLK1
I/PD
MII Transmit Clock Input:
Please references section 2.1.1.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AX88760 | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88760 Product Introduction |
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| AX88772_07 | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to 10/100 Fast Ethernet/HomePNA Controller |
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