參數(shù)資料
型號(hào): AX88196
廠商: Electronic Theatre Controls, Inc.
英文描述: 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM
中文描述: 一個(gè)10/100Base 3合1本地CPU總線快速以太網(wǎng)控制器與嵌入式靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù): 21/42頁(yè)
文件大?。?/td> 594K
代理商: AX88196
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
21
4.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
FIELD
NAME
7
-
Reserved
6:0
IFG
Inter-frame Gap. Default value 15H.
DESCRIPTION
4.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
FIELD
NAME
7
-
Reserved
6:0
IFG
Inter-frame Gap Segment 1. Default value 0cH.
DESCRIPTION
4.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
FIELD
NAME
7
-
Reserved
6:0
IFG
Inter-frame Gap Segment 2. Default value 11H.
DESCRIPTION
4.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)
FIELD
NAME
7
EECLK EECLK
EEPROM Clock
6
EEO
EEO
EEPROM Data Out
5
EEI
EEI
EEPROM Data In
4
EECS
EECS
EEPROM Chip Select
3
MDO
MDO
MII Data Out
2
MDI
MDI
MII Data In
1
MDIR
MII STA MDIO signal Direction
MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit
let MDIO as output signal.
0
MDC
MDC
MII Clock
DESCRIPTION
4.13 Test Register (TR) Offset 15H (Write)
FIELD
NAME
7
-
Reserved
6
MPSEL Media Priority Select : default value is logic 0
MPSEL /SLINK Media Selected
0 0 SNI
0 1 MII
1 x Depand on MPSET bit
5
MPSET Media Set by Program : The signal is valid only when MPSEL is set to high.
When MPSET is logic 0 , SNI is selected.
When MPSET is logic 1 , MII is selected.
4
TF16T
Test for Collision, default value is logic 0
3
TPE
Test pin Enable, default value is logic 0
2:0
IFG
Select Test Pins Output, default value is logic 0
DESCRIPTION
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