- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375384 > AX88190P (ASIX Electronics Corporation) 10/100BASE PCMCIA Fast Ethernet MAC Controller PDF資料下載
參數(shù)資料
| 型號： | AX88190P |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | 10/100BASE PCMCIA Fast Ethernet MAC Controller |
| 中文描述： | 一個10/100Base的PCMCIA快速以太網(wǎng)MAC控制器 |
| 文件頁數(shù)： | 8/41頁 |
| 文件大?。?/td> | 465K |
| 代理商： | AX88190P |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
AX88190 PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
8
2.2 EEPROM Signals Group
SIGNAL
TYPE
O
O
O
I/PU
PIN NO.
106
107
108
109
DESCRIPTION
EECS
EECK
EEDI
EEDO
EEPROM Chip Select : EEPROM chip select signal.
EEPROM Clock : Signal connected to EEPROM clock pin.
EEPROM Data In : Signal connected to EEPROM data input pin.
EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab - 2 EEPROM bus interface signals group
2.3 MII interface signals group
SIGNAL
TYPE
I
PIN NO.
90 – 87
DESCRIPTION
RXD[3:0]
Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
Collision : this signal is driven by PHY when collision is detected.
Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
Station Management Data Input / Output : Serial data input/output
transfers from/to the PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
CRS
I
85
RX_DV
I
83
RX_ER
I
82
RX_CLK
I
86
COL
TX_EN
I
84
95
O
TXD[3:0]
O
99 – 96
TX_CLK
I
94
MDC
O
92
MDIO
I/O/PU
91
Tab - 3 MII interface signals group
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX88195P | 10/100BASE Local CPU Bus Fast Ethernet MAC Controller |
| AX88196BLF | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface |
| AX88658AB | 8-Port 10/100/1000BASE-T Ethernet Switch |
| AX88772_07 | USB to 10/100 Fast Ethernet/HomePNA Controller |
| AX88772 | USB to 10/100 Fast Ethernet/HomePNA Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88195P | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE Local CPU Bus Fast Ethernet MAC Controller |
| AX88196 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| AX88196BLF | 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface |
| AX88196L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| AX88613 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。