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參數(shù)資料
| 型號： | AX88172L |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | USB to Fast Ethernet/HomePNA Controller |
| 中文描述： | USB到快速以太網(wǎng)/電話線網(wǎng)絡控制器 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 243K |
| 代理商： | AX88172L |
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ASIX ELECTRONICS CORPORATION
7
AX88172 PRELIMINARY
TX_EN
O
30
Transmit Enable: TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
Power Supply for logic circuits: +3.3V DC.
Receive Clock: RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV, RXD[3:0] and
RX_ER signals from the PHY to the MII port of the MAC.
Receive Data: RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
Power Supply for logic circuits: +3.3V DC.
Receive Error: RX_ER is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
Receive Data Valid: RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
Power Supply: +0V DC or Ground Power.
Power Supply for logic circuits: +3.3V DC.
Test Pin: This pin for test purpose only.
Pull up the pin or keep no connection for normal operation.
Test Pin: This pin for test purpose only.
Pull up the pin or keep no connection for normal operation.
I/O/PU 46, 45, 44 General Purpose Input/ Output Pins.
O
47
Output for reset PHY active low
O
48
Output for reset PHY active high
P
49
Power Supply: +0V DC or Ground Power.
I/PD
50
For testing
I/PD
51
For testing
O
52
LED indicator: When link FS, drives logic high always. When link
HS, the pin drives logic low. and it will drives high/low a period when
line has activity (data transfer).
P
53
Power Supply for logic circuits: +3.3V DC.
I/PD
54
For testing
ID
55
For testing
O
56
EEPROM Chip Select: EEPROM chip select signal.
O
57
EEPROM Clock: Signal connected to EEPROM clock pin.
O
58
EEPROM Data In: Signal connected to EEPROM data input pin.
I/PD
59
EEPROM Data Out: Signal connected to EEPROM data output pin.
P
60
Power Supply: +0V DC or Ground Power.
P
61
Power Supply for logic circuits: +3.3V DC.
I/PU
62
This pin define the assert level of Reset (pin 72)
When =’1’ or NC, reset signal is active High
When =’0’, reset signal is active Low
I/PD
63, 64, 65,
66, 67
I
68
Sets the IQ mode
This pin is used during testing. It must be set to low in IQ
measurement mode.
0: IQ mode
1: Normal operation mode
P
69
Power Supply for logic circuits: +3.3V DC.
I/PD
70
External 60MHz input
I/PD
71
For testing (TESTMODE)
0: Normal operation mode
1: External clock Synchronization mode
VDD
RX_CLK
P
I
31
32
RXD[3:0]
VDD
RX_ER
I
36, 35, 34,
33
37
38
P
I
RX_DV
I
39
VSS
VDD
TEST0
P
P
40
41
42
I/PU
TEST1
I/PU
43
GPIO[2:0]
/PHYRST
PHYRST
VSS
NC
NC
LED
VDD
NC
NC
EECS
EECK
EEDI
EEDO
VSS
VDD
RST_TYPE
NC
For testing
ANA_XIQ
VDD
CLKI
TESTMODE
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AX88178 | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller |
| AX88178A | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88179 -- USB3.0 轉 10/100/1000M 千兆以太網(wǎng)控制芯片 |
| AX88178L | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller |
| AX88179 | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88179 -- USB3.0 轉 10/100/1000M 千兆以太網(wǎng)控制芯片 |
| AX88179QF | 制造商:ASIX Electronics Corporation 功能描述: |
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