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參數(shù)資料
| 型號： | AX88172L |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | USB to Fast Ethernet/HomePNA Controller |
| 中文描述： | USB到快速以太網(wǎng)/電話線網(wǎng)絡(luò)控制器 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 243K |
| 代理商： | AX88172L |
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ASIX ELECTRONICS CORPORATION
6
AX88172 PRELIMINARY
2.0 Signal Description
The following terms describe the AX88172 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I
Input
O
Output
I/O
Input/Output
OD
Open Drain
PU
PD
P
Internal Pull Up (100K)
Internal Pull Down (100K)
Power Pin
SIGNAL
TYPE
I
PIN NO.
1
DESCRIPTION
R1
Constant-votage pin
A 6.2K± 1% resistors is connected to AVSS. Be sure to make the line
between R1 and each resistor as short as possible.
Power supply pin for analog circuits +3.3V DC
Power supply pin for analog circuits Ground
Power supply pin for analog circuits Ground
USB data line Data+
Power supply pin for analog circuits Ground
USB data line Data-
Power supply pin for analog circuits Ground
Power supply pin for analog circuits +3.3V DC
Remote-wakeup trigger from external pin. It active low
and should be keep low over 2 clocks (12MHz)
For testing
For testing
Power Supply for logic circuits: +3.3V DC.
Station Management Data Clock: The timing reference for MDIO. All
data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
Station Management Data Input/Output: Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII specification.
For testing
For testing
For testing
For testing
Power Supply: +0V DC or Ground Power.
Power Supply for logic circuits: +3.3V DC.
Collision: this signal is driven by PHY when collision is detected.
No connection
Transmit Clock: TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
Carrier Sense: Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
Transmit Data: TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
AVDD
AVSS
AVSS
DP
AVSS
DM
AVSS
AVDD
/EXTWAKEUP
P
P
P
B
P
B
P
P
2
3
4
5
6
7
8
9
10
I/PU
NC
NC
VDD
MDC
B
B
P
O
11
12
13
14
MDIO
I/O/PU
15
NC
NC
NC
NC
VSS
VDD
COL
NC
TX_CLK
O
O
O
O
P
P
I
I
16
17
18
19
20
21
22
23
24
CRS
I
25
TXD[3:0]
O
29, 28, 27,
26
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88178 | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller |
| AX88178A | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88179 -- USB3.0 轉(zhuǎn) 10/100/1000M 千兆以太網(wǎng)控制芯片 |
| AX88178L | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller |
| AX88179 | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88179 -- USB3.0 轉(zhuǎn) 10/100/1000M 千兆以太網(wǎng)控制芯片 |
| AX88179QF | 制造商:ASIX Electronics Corporation 功能描述: |
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