參數(shù)資料
型號： AX88140AQ
廠商： Electronic Theatre Controls, Inc.
英文描述： Fast Ethernet MAC Controller
中文描述： 快速以太網(wǎng)MAC控制器
文件頁數(shù)： 12/46頁
文件大小： 467K
代理商： AX88140AQ
AX88140A
PRELIMINARY
ASIX ELECTRONICS CORPORATION
12
2.2 PCI interface group
SIGNAL
TYPE
PIN
NUMBER
FOR 160 PIN
12,
13,
15,
16,
18,
19,
21,
22,
26,
27,
28,
29,
31,
32,
36,
37,
56,
57,
58,
60,
61,
63,
64,
66,
68,
69,
71,
72,
74,
75,
77,
78
23,
44,
54,
67
PIN
NUMBER
FOR 144 PIN
10,
11,
13,
14,
16,
17,
19,
20,
24,
25,
26,
27,
29,
30,
34,
35,
50,
51,
52,
54,
55,
57,
58,
60,
62,
63,
65,
66,
68,
69,
71,
72
21,
38,
48,
61
DESCRIPTION
AD<31>
AD<30>
AD<29>
AD<28>
AD<27>
AD<26>
AD<25>
AD<24>
AD<23>
AD<22>
AD<21>
AD<20>
AD<19>
AD<18>
AD<17>
AD<16>
AD<15>
AD<14>
AD<13>
AD<12>
AD<11>
AD<10>
AD<9>
AD<8>
AD<7>
AD<6>
AD<5>
AD<4>
AD<3>
AD<2>
AD<1>
AD<0>
CBE#<3>
CBE#<2>
CBE#<1>
CBE#<0>
I/O
Address and data bits are multiplexed on the same pins. During the
address phase, the AD<31:0> contain a physical address (32 bits).
During, data phases, AD<31:0> contain 32 bits of data.
The AX88140A supports both read and write bursts (in master
operation only). Little and big endian byte ordering can be used.
I/O
BUS COMMAND and BYTE ENABLE Are multiplexed on the
same PCI pins. During the address phase of the transaction,
CBE#<3:0>ProvidetheBUSCOMMAND.Duringthedataphase,
CBE#<3:0> Provide the BYTE ENABLE. The BYTE ENABLE
determines which byte lines carry valid data., CBE#<0> Applies to
byte 0, and CBE#<3> Applies to byte 3.
Device select Is asserted by the target of the current bus access.
When the AX88140A is the master of the current bus access, the
target assert DEVSEL# confirming the access. It is driven by
AX88140A When AX88140A is selected as a slave.
The FRAME# Signal is driven by the AX88140A To indicate the
beginning and duration of an access. FRAME# Asserts to indicate
the beginning of a bus transaction. While FRAME# is asserted,
data transfers continue. When FRAME# deasserts the next data
phase is the final data phase transaction.
BUS GRANT Indicates to theAX88140A That accessto the busis
granted.
Initialization devise select asserts To indicate that the host is
issuing a configuration cycle to the AX88140A.
Interrupt request asserts When one of the appropriate bits of reg5
sets and causes an interrupt, provided that the corresponding mask
bit in reg7 is not asserted. interrupt request deasserts by writing a 1
into the appropriate crs5 bit.
This pin must be pulled up by an external resistor.
Initiator ready Indicates the bus master
current data phase of the transaction.
A data phase is completed on any rising edge of the clock When
both IRDY# and target ready TRDY# are asserted. Wait cycles are
inserted until both IRDY# and TRDY# are asserted together.
When the AX88140A is the bus master, IRDY# is asserted during
write operations to indicate that valid data is present on the
AD<31:0>. During read operations, the AX88140A asserts
DEVSEL#
I/O
48
42
FRAME#
I/O
45
39
GNT#
I
9
7
IDSEL
I
24
22
INT#
O/D
3
1
IRDY#
I/O
46
40
ability to complete the
相關(guān)PDF資料
PDF描述
AX88196 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM
AX88196L 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM
AX88796 3-in-1 Local Bus Fast Ethernet Controller
AX88796L 3-in-1 Local Bus Fast Ethernet Controller
AY3-8910 PROGRAMMABLE SOUND GENERATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX88141 制造商:ASIX 制造商全稱:ASIX 功能描述:100BASE-TX/FX PCI BUS FAST ETHERNET MAC CONTROLLER WITH POWER MANAGEMENT
AX88170L 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to Fast Ethernet/HomePNA Controller
AX88172 制造商:ASI 制造商全稱:ASI 功能描述:USB2.0 TO ETHERNET Device setup guide
AX88172A 制造商:ASIX 制造商全稱:ASIX 功能描述:USB 2.0 to 10/100M Fast Ethernet Controller
AX88172ATF 制造商:ASIX 制造商全稱:ASIX 功能描述:USB 2.0 to 10/100M Fast Ethernet Controller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*