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參數(shù)資料
| 型號： | AX500-2FGG676I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 28/262頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA AXCELERATOR 500K 676FBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Axcelerator |
| 邏輯元件/單元數(shù)： | 5376 |
| RAM 位總計： | 73728 |
| 輸入/輸出數(shù)： | 336 |
| 門數(shù)： | 500000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
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Axcelerator Family FPGAs
Re vi s i on 18
2 - 109
throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse
engineer the device by attempting to exploit either the programming or probing interfaces. Both invasive
and noninvasive attacks against an Axcelerator device that access or bypass these security fuses will
destroy access to the rest of the device. (refer to the Design Security in Nonvolatile Flash and Antifuse
white paper).
Look for this symbol to ensure your valuable IP is protected with highest level of security in the industry.
To ensure maximum security in Axcelerator devices, it is recommended that the user program the device
security fuse (SFUS). When programmed, the Silicon Explorer II testing probes are disabled to prevent
internal probing, and the programming interface is also disabled. All JTAG public instructions are still
accessible by the user.
For more information, refer to the Implementation of Security in Actel Antifuse FPGAs application note.
Global Set Fuse
The Global Set Fuse determines if all R-cells and I/O registers (InReg, OutReg, and EnReg) are either
cleared or preset by driving the GCLR and GPSET inputs of all R-cells and I/O Registers (Figure 2-31 on
page 2-58). Default setting is to clear all registers (GCLR = 0 and GPSET =1) at device power-up. When
the GBSETFUS option is checked during FUSE file generation, all registers are preset (GCLR = 1 and
GPSET= 0). A local CLR or PRESET will take precedence over this setting. Both pins are pulled High
during normal device operation. For use details, see the Libero IDE online help.
Silicon Explorer II Probe Interface
Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer
tools, allows users to examine any of the internal nets (except I/O registers) of the device while it is
operating in a prototype or a production system. The user can probe up to four nodes at a time without
changing the placement and routing of the design and without using any additional device resources.
Highlighted nets in Designer’s ChipPlanner can be accessed using Silicon Explorer II in order to observe
their real time values.
Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the
debug cycle. In addition, Silicon Explorer II does not require relayout or additional MUXes to bring signals
out to external pins, which is necessary when using programmable logic devices from other suppliers. By
eliminating multiple place-and-route program cycles, the integrity of the design is maintained throughout
the debug process.
Each member of the Axcelerator family has four external pads: PRA, PRB, PRC, and PRD. These can be
used to bring out four probe signals from the Axcelerator device (note that the AX125 only has two probe
signals that can be observed: PRA and PRB). Each core tile has up to two probe signals. To disallow
probing, the SFUS security fuse in the silicon signature has to be programmed (see "Special Fuses" on
Silicon Explorer II connects to the host PC using a standard serial port connector. Connections to the
circuit board are achieved using a nine-pin D-Sub connector (Figure 1-9 on page 1-7). Once the design
has been placed-and-routed, and the Axcelerator device has been programmed, Silicon Explorer II can
be connected and the Explorer software can be launched.
Silicon Explorer II comes with an additional optional PC hosted tool that emulates an 18-channel logic
analyzer. Four channels are used to monitor four internal nodes, and 14 channels are available to probe
external signals. The software included with the tool provides the user with an intuitive interface that
allows for easy viewing and editing of signal waveforms.
Figure 2-69 FuseLock Logo
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX500-2FG676I | IC FPGA AXCELERATOR 500K 676FBGA |
| A54SX32-1BG329I | IC FPGA SX 48K GATES 329-BGA |
| A54SX32-2BGG329 | IC FPGA SX 48K GATES 329-BGA |
| A54SX32-1BGG329I | IC FPGA SX 48K GATES 329-BGA |
| A54SX32-2BG329 | IC FPGA SX 48K GATES 329-BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX500-2FGG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX500-2FGG896B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX500-2FGG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX500-2FGG896M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX500-2FGG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
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