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參數(shù)資料
| 型號： | AV9110-02CN14 |
| 英文描述： | Serially Programmable Frequency Generator |
| 中文描述： | 串行可編程頻率發(fā)生器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 267K |
| 代理商： | AV9110-02CN14 |
AV9110
Output Divider Turth Tables
1
D
O
C
0
D
O
C
X
d
D
)
X
1
/
K
L
t
(
C
e
p
O
0
0
0
1
2
1
0
4
1
1
8
Table 2
1
D
O
C
0
D
O
C
O
D
)
C
V
t
(
e
d
p
O
R
1
0
0
0
1
2
1
0
4
1
1
8
Table 3
Programming the PLL
The AV9110 has a wide operating range but it is recommended that it is operated within the following limits:
The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
f
VCO
=
N
V
fREF
Where N = VCO divided, 3 to 127
M =m Reference divide, 3 to 127
V = Perscale, 1 or 8
The 2 output drivers then give the following frequencies:
f
CLK
=
f
VCO
R
=
N
V
fREF
or f
REF
(output mixable by bit 17)
f
CLK/X
=
=
f
VCLK
Where R, X = output dividers 1, 2, 4 or 8
f
VCO
R
X
Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will
give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.
f
<
z
H
M
2
F
E
R
z
H
M
2
3
<
f
F
E
R
y
c
n
e
u
q
e
e
n
e
t
p
n
=
z
H
M
5
<
<
z
H
k
0
0
2
7
2
1
o
3
,
d
e
n
e
R
=
M
f
<
z
H
M
0
5
O
C
V
z
H
M
0
5
2
<
f
O
C
V
y
c
n
e
u
q
e
t
p
o
O
C
V
=
f
O
C
V
z
H
M
0
5
2
<
f
K
L
C
y
c
n
e
u
q
e
t
p
o
X
/
K
L
C
r
K
L
C
=
f
REF
M
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