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參數(shù)資料
| 型號： | AUIRL7732S2TR1 |
| 元件分類： | JFETs |
| 英文描述： | 14 A, 40 V, 0.0066 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, ISOMETRIC-3 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 216K |
| 代理商： | AUIRL7732S2TR1 |
AUIRL7732S2TR/TR1
www.irf.com
7
Fig 17. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 16, 17:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 18a, 18b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7.
ΔT = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 16, 17).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav f
ZthJC(D, tav) = Transient thermal resistance, see figure 15)
PD (ave) = 1/2 ( 1.3BVIav) = DT/ ZthJC
Iav = 2DT/ [1.3BVZth]
EAS (AR) = PD (ave)tav
Fig 18b. Unclamped Inductive Waveforms
Fig 18a. Unclamped Inductive Test Circuit
tp
V(BR)DSS
IAS
Fig 19a. Gate Charge Test Circuit
Fig 19b. Gate Charge Waveform
VDS
90%
10%
VGS
td(on)
tr
td(off) tf
Fig 20a. Switching Time Test Circuit
Fig 20b. Switching Time Waveforms
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
VGS
1K
VCC
DUT
0
L
S
20K
VDS
Pulse Width ≤ 1 s
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
5
10
15
20
25
30
E
A
R
,A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 35A
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