參數(shù)資料
型號: AU5780D
廠商: NXP SEMICONDUCTORS
元件分類: 其它接口
英文描述: SAE/J1850/VPW transceiver
中文描述: SPECIALTY INTERFACE CIRCUIT, PDSO8
文件頁數(shù): 2/10頁
文件大?。?/td> 79K
代理商: AU5780D
Philips Semiconductors
Product specification
AU5780
SAE/J1850/VPW transceiver
2
1998 Jun 30
853–2087 19650
FEATURES
Supports SAE/J1850 VPW standard for in-vehicle class B
multiplexing
Bus speed 10.4 kbps nominal
Drive capability 32 bus nodes
Low RFI due to output waveshaping with adjustable slew rate
Direct battery operation with protection against +50V load dump,
jump start and reverse battery
Bus terminals proof against automotive transients up to
–200V/+200V
Thermal overload protection
Very low bus idle power consumption
Diagnostic loop-back mode
4X mode (41.6 kbps) reception capability
ESD protected to 9 KV on bus and battery pins
8-pin SOIC
DESCRIPTION
The AU5780 is a line transceiver being primarily intended for
in-vehicle multiplex applications. It provides interfacing between a
link controller and the physical bus wire. The device supports the
SAE/J1850 VPWM standard with a nominal bus speed of 10.4 kbps.
PIN CONFIGURATION
SL01196
1
2
3
4
8
7
6
SO8
5
TX
R/F
RX
GND
BATT
BUS_OUT
BUS_IN
/LB
AU5780
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
BATT.op
Operating supply voltage
6
12
24
V
T
A
Operating ambient temperature
–40
+125
°
C
V
BATT.ld
Battery voltage
load dump; 1s
+50
V
I
BATT.lp
Bus idle supply current
V
BATT
=12V
200
μ
A
V
B
Bus voltage
0 < V
BATT
< 24V
–20
+20
V
V
BOH
Bus output voltage
300
< R
L
< 1.6k
7.3
8.0
V
–I
BO.LIM
Bus output source current
0V < V
BO
< +8.5V
47
mA
V
BI
Bus input threshold
3.65
4.1
V
t
P
Propagation delay
Tx to Rx
16
24
μ
s
V
SR
Bus output slew rate
R
s
= 56 k
0.3
V/
μ
s
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
–40 to +125
°
C
ORDER CODE
AU5780D
DWG #
SOT96-1
SO8:
8-pin plastic small outline package; Packed in tubes
SO8:
8-pin plastic small outline package; Packed on tape & reel
–40 to +125
°
C
AU5780D–T
SOT96-1
相關(guān)PDF資料
PDF描述
AU5780D-T SAE/J1850/VPW transceiver
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