2011 Microchip Technology Inc.
DS39932D-page 325
PIC18F46J11 FAMILY
TABLE 19-4:
REGISTERS ASSOCIATED WITH I2C OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PMPIF(3)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PIE1
PMPIE(3)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
IPR1
PMPIP(3)
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
PIR2
OSCFIF
CM2IF
CM1IF
—BCL1IF
LVDIF
TMR3IF
CCP2IF
PIE2
OSCFIE
CM2IE
CM1IE
—BCL1IE
LVDIE
TMR3IE
CCP2IE
IPR2
OSCFIP
CM2IP
CM1IP
—BCL1IP
LVDIP
TMR3IP
CCP2IP
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CTMUIF
TMR3GIF
RTCIF
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CTMUIE TMR3GIE
RTCIE
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CTMUIP TMR3GIP
RTCIP
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
SSP1BUF
MSSP1 Receive Buffer/Transmit Register
SSPxADD
MSSP1 Address Register (I2C Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode)
SSPxMSK(1)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
SSPxCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
SSPxCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
GCEN
ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2)
SEN
SSPxSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
SSP2BUF
MSSP2 Receive Buffer/Transmit Register
SSP2ADD
MSSP2 Address Register (I2C Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode)
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used by the MSSPx module in I2C mode.
Note 1:
SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I2C Slave mode
2:
Alternate bit definitions for use in I2C Slave mode operations only.
3:
These bits are only available on 44-pin devices.