參數(shù)資料
        

        


        


        
型號：
ATWEBDVK-02WC

        

        
廠商：
Atmel

        

        
文件頁數(shù)：
122/137頁

        

        
文件大?。?/td>
0K

        

        
描述：
KIT DEV TCP/IP AT89C51RD2 WEBCAM

        

        
標準包裝：
1

        

        
系列：
@Web

        

        
主要目的：
*
        		

        

        
嵌入式：
*
        		

        

        
已用 IC / 零件：
AT89C51RD2
        		

        

        
主要屬性：
*
        		

        

        
次要屬性：
*
        		

        

        
已供物品：
板，帶網(wǎng)絡(luò) Webcam 模塊和軟件
        		

        

        
產(chǎn)品目錄頁面：
617 (CN2011-ZH PDF)
        		

        

        

        

	
        
    
    

    
        
	
        85
        4235K–8051–05/08
        AT89C51RD2/ED2
        Table 19-2.
        WDTPRG Register
        WDTPRG - Watchdog Timer Out Register (0A7h)
        Reset Value = XXXX X000
        19.2
        WDT during Power-down and Idle
        In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
        down mode the user does not need to service the WDT. There are 2 methods of exiting Power-
        down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
        to entering Power-down mode. When Power-down is exited with hardware reset, servicing the
        WDT should occur as it normally should whenever the AT89C51RD2/ED2 is reset. Exiting
        Power-down with an interrupt is significantly different. The interrupt is held low long enough for
        the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
        the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
        the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service
        routine.
        To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is bet-
        ter to reset the WDT just before entering powerdown.
        In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
        AT89C51RD2/ED2 while in Idle mode, the user should always set up a timer that will periodically
        exit Idle, service the WDT, and re-enter Idle mode.
        7
        6
        5
        4
        3
        2
        1
        0
        -
        S2
        S1
        S0
        Bit
        Number
        Bit
        Mnemonic
        Description
        7
        -
        Reserved
        The value read from this bit is undetermined. Do not try to set this bit.
        6
        -
        5
        -
        4
        -
        3
        -
        2
        S2
        WDT Time-out select bit 2
        1
        S1
        WDT Time-out select bit 1
        0
        S0
        WDT Time-out select bit 0
        S2
        S1 S0Selected Time-out
        0
        00
        (214 - 1) machine cycles, 16. 3 ms @ F
        OSCA =12 MHz
        0
        01
        (215 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz
        0
        10 (216 - 1) machine cycles, 65. 5 ms @ F
        OSCA=12 MHz
        0
        11
        (217 - 1) machine cycles, 131 ms @ F
        OSCA=12 MHz
        1
        00
        (218 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
        1
        01 (219 - 1) machine cycles, 542 ms @ F
        OSCA=12 MHz
        1
        10
        (220 - 1) machine cycles, 1.05 ms @ F
        OSCA=12 MHz
        1
        11
        (221 - 1) machine cycles, 2.09 ms @ FOSCA=12 MHz
        
    
        
    
    
        


        


        

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