參數(shù)資料
型號(hào): ATSAM3X8CA-CU
廠商: Atmel
文件頁(yè)數(shù): 59/71頁(yè)
文件大小: 0K
描述: IC MCU 2X256KB CORTEX-M3 100-BGA
標(biāo)準(zhǔn)包裝: 260
系列: SAM3X
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 84MHz
連通性: CAN,以太網(wǎng),I²C,IrDA,LIN,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 63
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
64
11057BS–ATARM–13-Jul-12
SAM3X/A
64
11057BS–ATARM–13-Jul-12
SAM3X/A
Automatic Window Comparison of Converted Values
Write Protect Registers
12.11 Digital-to-Analog Converter (DAC)
2 channels, 12-bit DAC
Up to 1 mega-sample conversion rate in single channel mode
Flexible conversion range
Multiple trigger sources for each channel
Built-in offset and gain calibration
Possibility to drive output to ground
Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H
stage)
Two PDCA channels
Power reduction mode
12.12 CAN Controller (CAN)
Fully Compliant with CAN 2.0 Part A and 2.0 Part B
Bit Rates up to 1Mbit/s
8 Object Oriented Mailboxes with the Following Properties:
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
– Object Configurable in Receive (with Overwrite or Not) or Transmit Modes
– Independent 29-bit Identifier and Mask Defined for Each Mailbox
– 32-bit Access to Data Registers for Each Mailbox Data Object
– Uses a CAN_SIZE_COUNTER-bit Timestamp on Receive and Transmit Messages
– Hardware Concatenation of ID Masked Bitfields To Speed Up Family ID Processing
16-bit Internal Timer for Timestamping and Network Synchronization
Programmable Reception Buffer Length up to 8 Mailbox Objects
Priority Management between Transmission Mailboxes
Autobaud and Listening Mode
Low Power Mode and Programmable Wake-up on Bus Activity or by the Application
Data, Remote, Error and Overload Frame Handling
12.13 Ethernet MAC (EMAC)
DMA Master on Receive and Transmit Channels
Compatible with IEEE Standard 802.3
10 and 100 Mbit/s operation
Full- and half-duplex operation
Statistics Counter Registers
MII (144-pin SAM3X)/RMII (all SAM3X) interface to the physical layer
Interrupt generation to signal receive and transmit completion
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