參數(shù)資料
型號(hào): ATSAM3U1EB-CU
廠商: Atmel
文件頁數(shù): 28/60頁
文件大?。?/td> 0K
描述: IC MCU 64KB CORTEX-M3 144-TFBGA
標(biāo)準(zhǔn)包裝: 184
系列: SAM3U
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 96MHz
連通性: EBI/EMI,I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 20K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b,8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LFBGA
包裝: 托盤
34
6430FS–ATARM–10-Feb-12
SAM3U Series
9.1.4
Boot Strategies
The system always boots at address 0x0. To ensure a maximum boot possibilities the memory
layout can be changed via GPNVM.
A general purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the
ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by
default.
GPNVM2 enables to select if Flash 0 or Flash 1 is used for the boot. Setting the GPNVM2 bit
selects the boot from Flash 1, clearing it selects the boot from Flash 0.
9.2
External Memories
The SAM3U offers an interface to a wide range of external memories and to any parallel
peripheral.
9.2.1
Static Memory Controller
8- or 16- bit Data Bus
Up to 24-bit Address Bus (up to 16 MBytes linear per chip select)
Up to 4 chips selects, Configurable Assignment
Multiple Access Modes supported
– Byte Write or Byte Select Lines
Multiple device adaptability
– Control signals programmable setup, pulse and hold time for each Memory Bank
Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
Slow Clock mode supported
9.2.2
NAND Flash Controller
Handles automatic Read/Write transfer through 4224 bytes SRAM buffer
DMA support
Supports SLC NAND Flash technology
Programmable timing on a per chip select basis
Programmable Flash Data width 8-bit or 16-bit
9.2.3
NAND Flash Error Corrected Code Controller
Integrated in the NAND Flash Controller
Single bit error correction and 2-bit Random detection.
Automatic Hamming Code Calculation while writing
– ECC value available in a register
Automatic Hamming Code Calculation while reading
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