參數(shù)資料
型號(hào): ATSAM3N0BA-MU
廠商: Atmel
文件頁(yè)數(shù): 35/60頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32KB CORTEX-M3 64-QFN
標(biāo)準(zhǔn)包裝: 260
系列: SAM3N
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 48MHz
連通性: I²C,IrDA,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 47
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b,D/A 1x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
40
11011BS–ATARM–22-Feb-12
SAM3N Summary
10.13 Chip Identification
Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
JTAG ID: 0x05B2E03F
10.14 UART
Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
10.15 PIO Controllers
3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79
I/O Lines
Each PIO Controller controls up to 32 programmable I/O Lines
Fully programmable through Set/Clear Registers
Multiplexing of four peripheral functions per I/O Line
For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change, rising edge, falling edge, low level and level interrupt
– Debouncing and Glitch filter
Table 10-1.
SAM3N Chip ID Register
Chip Name
CHIPID_CIDR
CHIPID_EXID
ATSAM3N4C (Rev A)
0x29540960
0x0
ATSAM3N2C (Rev A)
0x29590760
0x0
ATSAM3N1C (Rev A)
0x29580560
0x0
ATSAM3N4B (Rev A)
0x29440960
0x0
ATSAM3N2B (Rev A)
0x29490760
0x0
ATSAM3N1B (Rev A)
0x29480560
0x0
ATSAM3N4A (Rev A)
0x29340960
0x0
ATSAM3N2A (Rev A)
0x29390760
0x0
ATSAM3N1A (Rev A)
0x29380560
0x0
Table 10-2.
PIO available according to pin count
Version
48 pin
64 pin
100 pin
PIOA
21
32
PIOB
13
15
PIOC
--
32
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