參數(shù)資料
型號(hào)： ATSAM3N0BA-MU
廠商： Atmel
文件頁數(shù)： 27/60頁
文件大小： 0K
描述： IC MCU 32KB CORTEX-M3 64-QFN
標(biāo)準(zhǔn)包裝： 260
系列： SAM3N
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 48MHz
連通性： I²C，IrDA，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 47
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x10b，D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 托盤
33
11011BS–ATARM–22-Feb-12
SAM3N Summary
9.1.3.9
Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial
JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program-
ming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered
when TST and PA0 and PA1are tied low.
9.1.3.10
SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART0.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
9.1.3.11
GPNVM Bits
The SAM3N features three GPNVM bits that can be cleared or set respectively through the com-
mands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
.
9.1.4
Boot Strategies
The system always boots at address 0x0. To ensure a maximum boot possibilities the memory
layout can be changed via GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the
ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by
default.
Table 9-2.
General-purpose Non volatile Memory Bits
GPNVMBit[#]
Function
0
Security bit
1
Boot mode selection
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