參數(shù)資料
型號(hào): ATMEGA324PA-MUR
廠商: Atmel
文件頁數(shù): 10/54頁
文件大?。?/td> 0K
描述: MCU AVR 32KB FLASH 20 MHZ 44QFN
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 4,000
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
其它名稱: ATMEGA324PA-MUR-ND
PIC16C925/926
DS39544A-page 144
Preliminary
2001 Microchip Technology Inc.
15.2
DC Characteristics: PIC16C925/926 (Commercial, Industrial)
PIC16LC925/926 (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C
≤ TA ≤ +85°C for industrial
0°C
≤ TA ≤ +70°C for commercial
Operating voltage VDD range as described in DC spec
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
Input Low Voltage
VIL
I/O ports
D030
with TTL buffer
VSS
— 0.15VDD
V
For entire VDD range
Vss
0.8V
V
4.5V
≤ VDD ≤ 5.5V
D031
with Schmitt Trigger buffer
VSS
0.2VDD
V
D032
MCLR, OSC1 (in RC mode)
VSS
0.2VDD
V
D033
OSC1 (in XT, HS and LP)
VSS
0.3VDD
V
(Note 1)
Input High Voltage
VIH
I/O ports
D040
with TTL buffer
2.0
VDD
V4.5V
≤ VDD ≤ 5.5V
D040A
0.25VDD
+ 0.8V
VDD
V
For entire VDD range
D041
with Schmitt Trigger buffer
0.8VDD
VDD
V
D042
MCLR
0.8VDD
VDD
V
D042A
OSC1 (XT, HS and LP)
0.7VDD
VDD
V
(Note 1)
D043
OSC1 (in RC mode)
0.9VDD
VDD
V
D070
IPURB PORTB Weak Pull-up Current
50
250
400
AVDD = 5V, VPIN = VSS
Input Leakage Current
(Notes 2, 3)
D060
IIL
I/O ports
——
±1.0
A Vss ≤ VPIN ≤ VDD, Pin at hi-Z
D061
MCLR, RA4/T0CKI
——
±5
A Vss ≤ VPIN ≤ VDD
D063
OSC1
——
±5
A Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
Output Low Voltage
D080
VOL I/O ports
——
0.6
V
IOL = 4.0 mA, VDD = 4.5V
D083
OSC2/CLKOUT (RC osc mode)
——
0.6
V
IOL = 1.6 mA, VDD = 4.5V
D090
VOH
Output High Voltage
I/O ports (Note 3)
VDD - 0.7 ——
VIOH = -3.0 mA, VDD = 4.5V
D092
OSC2/CLKOUT (RC osc mode)
VDD - 0.7 ——
VIOH = -1.3 mA, VDD = 4.5V
Capacitive Loading Specs on
Output Pins
D100
COSC2 OSC2 pin
——
15
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
D102
CIO
CB
All I/O pins and OSC2 (in RC)
SCL, SDA in I2C mode
50
400
pF
D150
VDD Open Drain High Voltage
——
8.5
V
RA4 pin
Data in “Typ” column is at 5 V, 25
°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C925/926 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
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