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鎻忚堪锛� IC MCU 8BIT 32KB FLASH 44TQFP
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鏍稿績铏曠悊鍣細 AVR
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绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 1K x 8
RAM 瀹归噺锛� 2K x 8
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鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
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鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� ATMEGA324P-B15AZ-ND
PIC16(L)F1826/27
DS41391D-page 244
2011 Microchip Technology Inc.
25.4
I2C
MODE OPERATION
All MSSPx I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and 2 interrupt
flags interface the module with the PIC microcon-
troller and user software. Two pins, SDAx and SCLx,
are exercised by the module to communicate with
other external I2C devices.
25.4.1
BYTE FORMAT
All communication in I2C is done in 9-bit segments. A
byte is sent from a Master to a Slave or vice-versa, fol-
lowed by an Acknowledge bit sent back. After the 8th
falling edge of the SCLx line, the device outputting
data on the SDAx changes that pin to an input and
reads in an acknowledge value on the next clock
pulse.
The clock signal, SCLx, is provided by the master.
Data is valid to change while the SCLx signal is low,
and sampled on the rising edge of the clock. Changes
on the SDAx line while the SCLx line is high define
special conditions on the bus, explained below.
25.4.2
DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips I2C
specification.
25.4.3
SDAX AND SCLX PINS
Selection of any I2C mode with the SSPxEN bit set,
forces the SCLx and SDAx pins to be open-drain.
These pins should be set by the user to inputs by set-
ting the appropriate TRIS bits.
25.4.4
SDAX HOLD TIME
The hold time of the SDAx pin is selected by the
SDAHT bit of the SSPxCON3 register. Hold time is the
time SDAx is held valid after the falling edge of SCLx.
Setting the SDAHT bit selects a longer 300 ns mini-
mum hold time and may help on buses with large
capacitance.
TABLE 25-2:
I2C BUS TERMS
Note:
Data is tied to output zero when an I2C
mode is enabled.
TERM
Description
Transmitter
The device which shifts data out
onto the bus.
Receiver
The device which shifts data in
from the bus.
Master
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
Slave
The device addressed by the mas-
ter.
Multi-master
A bus with more than one device
that can initiate data transfers.
Arbitration
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDAx and SCLx lines are
high.
Active
Any time one or more master
devices are controlling the bus.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SSPxADD.
Write Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Read Request
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCLx low to stall communication.
Bus Collision
Any time the SDAx line is sampled
low by the module while it is out-
putting and expected high state.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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