參數(shù)資料
型號: ATMEGA16A-AUR
廠商: Atmel
文件頁數(shù): 12/88頁
文件大?。?/td> 0K
描述: MCU AVR 16KB FLASH 16MHZ 44TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 2,000
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 帶卷 (TR)
其它名稱: ATMEGA16A-AUR-ND
2009 Microchip Technology Inc.
DS41288F-page 111
PIC16F610/616/16HV610/616
12.2
Calibration Bits
The 8 MHz internal oscillator is factory calibrated.
These calibration values are stored in fuses located in
the Calibration Word (2008h). The Calibration Word is
not erased when using the specified bulk erase
sequence in the Memory Programming Specification
(DS41284) and thus, does not require reprogramming.
12.3
Reset
The
PIC16F610/616/16HV610/616
differentiates
between various kinds of Reset:
a)
Power-on Reset (POR)
b)
WDT Reset during normal operation
c)
WDT Reset during Sleep
d)
MCLR Reset during normal operation
e)
MCLR Reset during Sleep
f)
Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
Power-on Reset
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
WDT wake-up does not cause register resets in the
same manner as a WDT Reset since wake-up is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 12-2. Software can use
these bits to determine the nature of the Reset. See
Table 12-4 for a full description of Reset states of all
registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 12-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 15.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR/VPP pin
VDD
OSC1/
WDT
Module
POR
Detect
OST/PWRT
On-Chip
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Reset
Enable OST
Enable PWRT
Sleep
Brown-out(1)
Reset
BOREN
CLKI pin
Note
1:
Refer to the Configuration Word register (Register 12-1).
RC OSC
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