Single Compare Unit Counter
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鍨嬭櫉锛� ATMEGA169PV-8MCU
寤犲晢锛� Atmel
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鏂囦欢澶у皬锛� 0K
鎻忚堪锛� MCU AVR 16K ISP FLASH 8MHZ 64QFN
鐢㈠搧鍩硅〒妯″锛� megaAVR Introduction
妯欐簴鍖呰锛� 260
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 8MHz
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 54
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绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 512 x 8
RAM 瀹归噺锛� 1K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
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宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-VQFN 闆欐帓瑁搁湶鐒婄洡
鍖呰锛� 鎵樼洡
閰嶇敤锛� ATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFP
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATJTAGICE2-ND - AVR ON-CHIP D-BUG SYSTEM
ATAVRBFLY-ND - KIT EVALUATION AVR BUTTERFLY
ATSTK502-ND - MOD EXPANSION AVR STARTER 500
ATSTK500-ND - PROGRAMMER AVR STARTER KIT
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91
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ATmega169P
14. 8-bit Timer/Counter0 with PWM
14.1
Features
Single Compare Unit Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
External Event Counter
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)
14.2
Overview
Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simpli-
fied block diagram is shown in Figure 14-1. For the actual placement of I/O pins, refer to Figure
1-1 on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
The device-specific I/O Register and bit locations are listed in the 鈥�8-bit Timer/Counter Register
Figure 14-1. 8-bit Timer/Counter Block Diagram
14.2.1
Registers
The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter-
rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt
Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg-
ister (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
T0).
Timer/Counter
D
ATA
B
U
S
=
TCNTn
Waveform
Generation
OCn
= 0
Control Logic
= 0xFF
BOTTOM
count
clear
direction
TOVn
(Int.Req.)
OCRn
TCCRn
Clock Select
Tn
Edge
Detector
( From Prescaler )
clkTn
TOP
OCn
(Int.Req.)
鐩搁棞PDF璩囨枡
PDF鎻忚堪
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