參數(shù)資料
型號: ATMEGA1284P-MUR
廠商: Atmel
文件頁數(shù): 45/160頁
文件大?。?/td> 0K
描述: MCU AVR 128KB FLASH 20MHZ 44VQFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝: 4,000
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
配用: ATSTK600-ND - DEV KIT FOR AVR/AVR32
其它名稱: ATMEGA1284P-MUR-ND
139
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
16.12.11 ICR3H and ICR3L – Input Capture Register 3
The Input Capture is updated with the counter (TCNT3) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter3). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
16.12.12 TIMSK1 – Timer/Counter1 Interrupt Mask Register
Bit 7:6 – Reserved
These bits are unused and will always read as zero.
Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 61) is executed when the ICF1 Flag, located in TIFR1, is set.
Bit 4:3 – Reserved
These bits are unused and will always read as zero.
Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1B Flag, located in
TIFR1, is set.
Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1A Flag, located in
TIFR1, is set.
Bit
76543210
(0x97)
ICR3[15:8]
ICR3H
(0x96)
ICR3[7:0]
ICR3L
Read/Write
R/W
Initial Value
00000000
Bit
7
65
43
2
1
0
–ICIE1
OCIE1B
OCIE1A
TOIE1
TIMSK1
Read/Write
R
R/W
R
R/W
Initial Value
0
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