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參數(shù)資料
| 型號： | ATM UTOPIA |
| 廠商： | Lineage Power |
| 英文描述： | Slave Core V2.0(異步傳輸模式從屬內(nèi)核V2.0) |
| 中文描述： | 奴隸核心2.0（異步傳輸模式從屬內(nèi)核2.0） |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 115K |
| 代理商： | ATM UTOPIA |
Product Brief
August 2000
ATM UTOPIA Slave Core V2.0
Features
I
UTOPIA Level 1/Level 2 with parity generation/
checking. In Level 2, all multi-PHY modes are sup-
ported:
— 1 RxClav/1 TxClav
— Direct status
— Multiplexed status polling
I
8-/16-bit bus width
I
Programmable cell length
I
25/33/50 MHz operation
I
Meets all UTOPIA setup and clock-to-output speci-
fications
I
FIFO control/monitoring with the following options:
— Internal 128
×
9/64
×
17 ORCA
FIFOs (scal-
able)
I
Flexible control inputs with options for the follow-
ing:
— Internal/external hardwiring
— Access via a parallel or serial microprocessor
interface
I
Supports the ORCA Series 2 and Series 3 families
of FPGAs
Standards Compliance
I
ATM forum UTOPIA Level 1 version 2.1
I
ATM forum UTOPIA Level 2 version 1.0
Benefits
I
Faster development for improved time-to-market
with ATM functions
I
Lower development cost through design reuse
I
VHDL* source code for easy design integration
I
ORCA-specific optimization, tailor-made for high
performance
I
Ample design flexibility using built-in interface and
function options
I
Verified functionality and standards compliance
0390(F)
Figure 1. ATM UTOPIA Slave Core Application
Description
The ATM UTOPIA Slave Core from Modelware
implements, in modular VHDL, the ATM forum's
UTOPIA Level 1 and Level 2 specifications.
The core interfaces to the application (e.g., ATM
physical or adaptation layer) via a generic FIFO-like
access interface and to the ATM layer via a UTOPIA
Level 1 or Level 2 interface (Figure 1). The core uses
internal FIFOs for cell buffering and timing transfer
between the application and the ATM layer.
The core (using 18-bit internal FIFOs) operates at
50 MHz in an OR2T15A-6 or an OR3T55-7 ORCA
FPGA.
* VHDLis a registered trademark of Gateway Design Automation
Corporation.
Modelwareis a registered trademark of Modelware, Inc.
UTOPIA
SLAVE
CORE
ACCESS
INTERFACE
UTOPIA
ATM
LAYER
FUNCTION
APPL.
(E.G., PHY
OR AAL)
C
S
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