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參數(shù)資料
| 型號(hào)： | ATM |
| 廠商： | Lineage Power |
| 英文描述： | Physical Layer Core(異步傳輸模式物理層內(nèi)核) |
| 中文描述： | 物理層核心（異步傳輸模式物理層內(nèi)核） |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 118K |
| 代理商： | ATM |
Product Brief
August 2000
ATM Physical Layer Core
Features
I
ATM header error correction (HEC) byte genera-
tion/checking
I
HEC-based cell delineation
I
Cell header single error correction/multiple error
detection
I
Cell payload (de)scrambling
I
Direct cell mapping
I
Idle cell insertion/deletion
I
Out of cell delineation (OCD)/loss of cell delinea-
tion (LCD) status
I
User-programmable cell filter
I
UTOPIA Level 1/Level 2 with parity generation/
checking. In Level 2, all multiPHY modes are sup-
ported:
— 1 RxClav/1 TxClav
— Direct status
— Multiplexed status polling
I
155.52 Mbits/s line operation
I
25 MHz UTOPIA operation (up to 50 MHz
stand-alone UTOPIA)
I
FIFO control/monitoring with options:
— Internal 128 x 9 ORCA
FIFOs (scalable)
— External 2
n
x 9 IDT722x1FIFOs
I
Flexible control inputs with options for:
— Internal/external hard-wiring
— Access via a parallel or serial microprocessor
interface
Standards Compliance
I
ANSI* T1.646-1995: Broadband-ISDN Physical
Layer Specification for User-Network Interface
Including DS1/ATM
I
Asynchronous transfer mode (ATM) forum user-
network interface (UNI) version 3.1
I
ATM forum UTOPIA, An ATM-PHY interface speci-
fication level 1, version 2.01
I
ATM forum UTOPIA Level 2, version 1.0
I
ITU-T recommendation I.432: B-ISDN user-net-
work interface physical layer specification
Benefits
I
Faster development for improved time-to-market
with ATM functions.
I
Lower development cost through design reuse.
I
VHDL source code for easy design integration.
I
ORCA-specific optimization, tailor made for high
performance.
I
Ample design flexibility using built-in interface and
function options.
I
Verified functionality and standards compliance.
0378 (F)
Figure 1. ATM Physical Layer Core Application
* ANSIis a registered trademark of American National Standards
Institute, Inc.
ATM
PHYSICAL
LAYER
CORE
ATM
LAYER
LINE
FRAMER
(E.G.,
SONET)
OPTIONAL
EXTERNAL
FIFO
OPTIONAL
CONTROL/STATUS
INTERFACE
LINE
BYTE
DATA AND
CLOCK
UTOPIA
MICROPROCESSOR BUS
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