參數(shù)資料
型號： ATF2500C-15JU
廠商： Atmel
文件頁數(shù)： 18/24頁
文件大?。?/td> 0K
描述： IC CPLD EE 15NS 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： ATF2500C(L)
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 15.0ns
電壓電源 - 內(nèi)部： 4.5 V ~ 5.5 V
宏單元數(shù)： 24
輸入/輸出數(shù)： 24
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC
包裝： 管件
產(chǎn)品目錄頁面： 608 (CN2011-ZH PDF)
3
0777K–PLD–1/24/08
ATF2500C
3.
Using the ATF2500C Family’s Many Advanced Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
Fully Connected Logic Array – Each array input is always available to every product term.
This makes logic placement a breeze.
Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also
easily created. These options allow more efficient product term usage.
Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to feed
its input (D/T2) directly back to the logic array. This provides further logic expansion capability
without using precious pin resources.
Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops has
a dedicated clock product term. This removes the constraint that all registers use the same
clock. Buried state machines, counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock source selection further allows mixing
higher performance pin clocking and flexible product term clocking within one design.
A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of 48.
Each register has its own clock and reset terms, as well as its own sum term.
Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a dedicated
input path. Each of the 48 registers has its own feedback term into the array as well. These
features, combined with individual product terms for each I/O’s output enable, facilitate true
bi-directional I/O design.
Combinable Sum Terms – Each output macrocell’s three sum terms may be combined into
a single term. This provides a fan in of up to 12 product terms per sum term with no speed
penalty.
Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus
interfacing applications. Floating pins can be set to a known state if the Pin-keepers are
enabled.
User Row (64 bits) – Use to store information such as unit history.
相關(guān)PDF資料
PDF描述
TAS685K050P1F-F CAP TANT 6.8UF 50V 10% AXIAL
HMC31DRES-S734 CONN EDGECARD 62POS .100 EYELET
ATF750C-7SX IC CPLD 7NS 24SOIC
HCC49DRES-S734 CONN EDGECARD 98POS .100 EYELET
TAS156K050P1F-F CAP TANT 15UF 50V 10% AXIAL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATF2500C-15JU SL383 制造商:Atmel Corporation 功能描述:ATF2500C 1.5K GATES 24 MC IND EEPROM 5V 44 PLCC - Tape and Reel
ATF2500C-20GM 功能描述:CPLD - 復(fù)雜可編程邏輯器件 2500 Gates 5.0V CPLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF2500C-20JC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 2500 GATE 24 MACRO STD PWR 5V-20NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF2500C-20JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 2500 GATE 24 MACRO STD PWR 5V-20NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF2500C-20KM 功能描述:CPLD - 復(fù)雜可編程邏輯器件 STD PWR 2500 GATE 24 MACROCELL 5V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*