參數(shù)資料
型號(hào)： ATF1508RE-5AX100
廠商： Atmel
文件頁數(shù)： 2/31頁
文件大小： 0K
描述： IC CPLD 128MC 3.3V ISP 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： ATF15xx
可編程類型： 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)）
最大延遲時(shí)間 tpd(1)： 7.0ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
宏單元數(shù)： 128
輸入/輸出數(shù)： 80
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
10
3682A–PLD–10/08
ATF1508RE
2.6
On-Chip Voltage Regulator
The ATF1508RE CPLD device has a built-in Internal Voltage Regulator that converts an exter-
nal 3.3V supply to internal 1.8V core supply. The 1.8V output of the internal voltage regulator is
also connected to the VCCIRO pin (Pin 39 for 100-pin TQFP) so that external bypass capacitors
can be used to minimize noise. The recommended bypass capacitor values for the VCCIRO pin
are 2.2 F or 4.7 F X7R, and 470 pF or 1 nF NPO type. These capacitors will help filter out
noise at the output of the internal voltage regulator, which is important for the ATF1508RE to
operate properly (see Figure 2-3).
The ATF1508RE CPLD also supports MultiVolt I/O interface feature, which allows seamless
interface to other devices at 1.5V, 1.8V, 2.5V, or 3.3V logic levels. The ATF1508RE device has
two I/O banks, each bank can be supplied with an independent VCCIO (VCCIOA or VCCIOB).
Figure 2-3.
On-Chip Voltage Regulator
3.
Power Management
Unlike conventional CPLDs with sense amplifiers, the ATF1508RE is designed using low-power
full CMOS design techniques. This enables the ATF1508RE to achieve extremely low power
consumption over the full operating frequency spectrum.
The ATF1508RE also has an optional power-down mode. In this mode, current drops to below
100 A. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used
to power down the part. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any
enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s mac-
rocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins.
4.
Security Feature
A fuse is provided to prevent unauthorized copying of the ATF1508RE fuse patterns. Once
enabled, fuse reading or verification is inhibited. However, the 16-bit User Electronic Signature
remains accessible. To reset this feature, the entire memory array in the device must be erased.
1.8V
ATF1508RE
Core
Logic
470 pF
or
1 nF
V
CCIRI = 3.3V
Pin 91 for 100 TQFP
Internal
Voltage
Regulator
V
CCIRO = 1.8V
Pin 39 for 100 TQFP
2.2 F
or
4.7 F
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