參數(shù)資料
型號: ATF1508RE-5AX100
廠商: Atmel
文件頁數(shù): 16/31頁
文件大?。?/td> 0K
描述: IC CPLD 128MC 3.3V ISP 100TQFP
標準包裝: 90
系列: ATF15xx
可編程類型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 7.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
宏單元數(shù): 128
輸入/輸出數(shù): 80
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
23
3682A–PLD–10/08
ATF1508RE
13. ATF1508RE Dedicated Pinouts
OE (1, 2)
Global OE pins
GCLR
Global Clear pin
GCLK (1, 2, 3)
Global Clock pins
PD (1, 2)
Power-down pins
TDI, TMS, TCK, TDO
JTAG pins used for boundary-scan testing or in-system
programming
GND
Ground pins
V
CCIRI
Core VCC input pin for the device regulator (+3.0V - 3.6V)
V
CCIOA
LAB A and B – V
CC supply pins for I/Os (1.5V, 1.8V, 2.5V,
or 3.3V)
V
CCIOB
LAB C and D – V
CC supply pins for I/Os (1.5V, 1.8V, 2.5V,
or 3.3V)
V
REFA
Reference voltage pin for SSTL inputs in bank A
V
REFB
Reference voltage pin for SSTL inputs in bank B
VCCIRO
Output pin of the regulator to be used for capacitor coupling only.
Table 13-1.
ATF1508RE Dedicated Pinouts
Dedicated Pin
132-ball CBGA
100-lead TQFP
INPUT / OE2 / GCLK2
C3
90
INPUT / GCLR
A3
89
INPUT / OE1
C2
88
INPUT / GCLK1
L2
87
I/O / GCLK3
M8
85
I/O / PD (1,2)
F1, G12
1, 41
I/O / VREFA
H1
12
I/O / V
REFB
L13
60
I/O / TDI (JTAG)
M9
4
I/O / TMS (JTAG)
N10
15
I/O / TCK (JTAG)
M10
62
I/O / TDO (JTAG)
B9
73
GND
A9, B14, B3, E14, H14, J14, K2, N1, N9,
N12, P4
11, 26, 38, 43, 59, 74, 86, 95
VCCIRI
K12, A2
91
VCCIRO
P1
39
V
CCIOA
J3, P7, P13, G14
3, 18, 34
VCCIOB
A7, A14, C4
51, 66, 82
N/C
L1, L3, M1, N4, C13, B10, D3, P6, P8, N2,
N7, N8, M7, M2, M12, M13, M14, C7, C8,
C14, B6, B7, B8, B13, A6, A8, A13
# of Signal Pins
84
# User I/O Pins
80
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