參數(shù)資料
型號(hào): ATA5744N-TKSY
廠商: ATMEL CORP
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: LEAD FREE, SSO-20
文件頁(yè)數(shù): 20/20頁(yè)
文件大?。?/td> 316K
代理商: ATA5744N-TKSY
9
4893A–RKE–11/05
ATA5744
4.6
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock.
According to Figure 4-3, this clock cycle TClk is derived from the crystal oscillator (XTO) in com-
bination with a divider. The division factor is controlled by the logical state at pin MODE.
According to chapter 'RF Front End', the frequency of the crystal oscillator (f
XTO) is defined by
the RF input signal (f
RFin) which also defines the operating frequency of the local oscillator (fLO).
Figure 4-3.
Generation of the Basic Clock Cycle
Pin MODE can now be set in accordance with the desired clock cycle T
Clk. TClk controls the fol-
lowing application-relevant parameters:
Timing of the analog and digital signal processing
IF filter center frequency (f
IF0)
Most applications are dominated by two transmission frequencies: f
Send = 315 MHz is mainly
used in USA, f
Send = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent
parameters, the electrical characteristics display three conditions for each parameter.
Application USA
(f
XTO = 4.90625 MHz, MODE = L, TClk = 2.0383 s)
Application Europe
(f
XTO = 6.76438 MHz, MODE = H, TClk = 2.0697 s)
Other applications
(T
Clk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic
is given as a function of T
Clk).
The clock cycle of some function blocks depends on the selected baud rate range (BR_Range)
which is defined by the pins BR_0 and BR_1. This clock cycle T
XClk is defined by the following
formulas for further reference:
BR_Range = BR_Range0:
T
XClk = 8 × TClk
BR_Range1:
T
XClk = 4 × TClk
BR_Range2:
T
XClk = 2 × TClk
BR_Range3:
T
XClk = 1 × TClk
DVCC
XTO
MODE
16
15
14
T
Clk
f
XTO
Divider
:14/:10
L : USA(:10)
H: Europe(:14)
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