參數(shù)資料
型號(hào): ATA5728P6-TKQY
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: SSOP-20
文件頁數(shù): 18/46頁
文件大?。?/td> 776K
代理商: ATA5728P6-TKQY
25
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
11. Configuring the Receiver
The ATA5723/ATA5724/ATA5728 receiver is configured using two 12-bit RAM registers called
OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA
port. If the register content has changed due to a voltage drop, this condition is indicated by a
the output pattern called reset marker (RM). If this occurs, the receiver must be reprogrammed.
After a Power-On Reset (POR), the registers are set to default mode. If the receiver is operated
in default mode, there is no need to program the registers. Table 11-3 on page 25 shows the
structure of the registers. According to Table 11-1, bit 1 defines whether the receiver is set back
to polling mode using the OFF command (see “Receiving Mode” on page 15) or whether it is
programmed. Bit 2 represents the register address. It selects the appropriate register to be pro-
grammed. For high programming reliability, bit 15 (Stop bit), at the end of the programming
operation, must be set to 0.
Table 11-1.
Effect of Bit 1 and Bit 2 on Programming the Registers
Bit 1
Bit 2
Action
1
x
The receiver is set back to polling mode (OFF command)
0
1
The OPMODE register is programmed
0
The LIMIT register is programmed
Table 11-2.
Effect of Bit 15 on Programming the Register
Bit 15
Action
0
The values are written into the register (OPMODE or LIMIT)
1
The values are not written into the register
Table 11-3.
Effect of the Configuration Words within the Registers
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
OFF command
1–
OPMODE register
01
BR_Range
N
Bit-check
Modu-
lation
Sleep
X
Sleep
Noise
Suppression
0
Baud1
Baud0
BitChk1
BitChk0
ASK/
_FSK
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
X
SleepStd
Noise_
Disable
Default
values of
Bit 3...14
00
0
1
0
1
0
1
LIMIT register
00
Lim_min
Lim_max
Lim_
min5
Lim_
min4
Lim_
min3
Lim_
min2
Lim_
min1
Lim_
min0
Lim_
max5
Lim_
max4
Lim_
max3
Lim_
max2
Lim_
max1
Lim_
max0
0
Default
values of
Bit 3...14
01
0
1
0
1
0
1
0
1
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